Abstract: A simulated battery test device and method that is capable of testing a battery charging circuit and logic circuit to determine proper operation. An operational amplifier is used that can both source and sink current to simulate the operation of the battery. A battery low signal can be generated using the simulated battery test device to test a battery charging circuit and logic circuit in a battery low condition. In addition, a battery open signal can be generated to test the battery charging and logic circuit in a battery open condition. Charging currents are detected to determine if currents fall within an acceptable range.

Abstract: A simulated battery test device and method that is capable of testing a battery charging circuit and logic circuit to determine proper operation. An operational amplifier is used that can both source and sink current to simulate the operation of the battery. A battery low signal can be generated using the simulated battery test device to test a battery charging circuit and logic circuit in a battery low condition. In addition, a battery open signal can be generated to test the battery charging and logic circuit in a battery open condition. Charging currents are detected to determine if currents fall within an acceptable range.

Abstract: A simulated battery test device and method that is capable of testing a battery charging circuit and logic circuit to determine proper operation. An operational amplifier is used that can both source and sink current to simulate the operation of the battery. A battery low signal can be generated using the simulated battery test device to test a battery charging circuit and logic circuit in a battery low condition. In addition, a battery open signal can be generated to test the battery charging and logic circuit in a battery open condition. Charging currents are detected to determine if currents fall within an acceptable range.

Abstract: A storage controller for redundant arrays of independent disks (RAID) comprises a daughter card containing a standardized controller core, which is mated to one of a number of customizable controller interface cards. The controller core card includes high performance elements such as a processor, cache memory, CRC circuitry, a host port, and a storage port. All operational communication with non-core components occurs via the host port and the storage port through the controller interface card. The controller core card monitors and configures communications between the host and the storage array. Each controller interface card is populated with components and connectors particular to the respective application or RAID system. The size and layout of the controller interface card may also be customized to the particular application. Sharing the same controller core card among various RAID controllers lowers the cost and time-to-market for customized RAID systems.

Abstract: A storage controller for redundant arrays of independent disks (RAID) comprises a daughter card containing a standardized controller core, which is mated to one of a number of customizable controller interface cards. The controller core card includes high performance elements such as a processor, cache memory, CRC circuitry, a host port, and a storage port. All operational communication with non-core components occurs via the host port and the storage port through the controller interface card. The controller core card monitors and configures communications between the host and the storage array. Each controller interface card is populated with components and connectors particular to the respective application or RAID system. The size and layout of the controller interface card may also be customized to the particular application. Sharing the same controller core card among various RAID controllers lowers the cost and time-to-market for customized RAID systems.

Abstract: A dual disk drive peripheral data storage system is disclosed. The dual disk drive is a combination of a hard disk drive and a solid state disk drive whereby the solid state buffer memory that is typically used as a data cache for the hard disk drive is partitioned such that one portion provides the memory for the solid state disk drive while another portion remains as the cache for the hard disk. The dual disk drive provides the capability for a user to repartition the solid state buffer memory such that the sizes of the solid state disk drive memory and cache memory can be adjusted to increase the data transfer rate with a host computational system.