Patents by Inventor Randall J. Pascarella

Randall J. Pascarella has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for ordering interconnect transactions in a computer system
    Patent number: 6941407
    Abstract: A system allows queuing interconnect transactions of a first transaction type and a second transaction type according to an interconnect protocol for a computer system in a transaction order queue (TOQ). The queuing technique imposes an additional ordering on interconnect transactions in addition to ordering rules of the interconnect protocol. Transactions can bypass the TOQ if no transactions of the first type are awaiting execution or are in the TOQ. Transactions are dequeued from the TOQ if no transactions of either the first transaction type or the second transaction type are awaiting scheduling for execution.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: September 6, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Paras A. Shah, Ryan J. Hensley, Randall J. Pascarella
  • Method and apparatus for ordering interconnect transactions in a computer system
    Publication number: 20040064626
    Abstract: A system allows queuing interconnect transactions of a first transaction type and a second transaction type according to an interconnect protocol for a computer system in a transaction order queue (TOQ). The queuing technique imposes an additional ordering on interconnect transactions in addition to ordering rules of the interconnect protocol. Transactions can bypass the TOQ if no transactions of the first type are awaiting execution or are in the TOQ. Transactions are dequeued from the TOQ if no transactions of either the first transaction type or the second transaction type are awaiting scheduling for execution.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 1, 2004
    Applicant: Compaq Information Technologies Group, L.P.
    Inventors: Paras A. Shah, Ryan J. Hensley, Randall J. Pascarella
  • SCSI duplex-ready backplane for selectively enabling SCSI simplex and duplex modes based on indication of desired SCSI mode
    Patent number: 6055582
    Abstract: A computer system with a SCSI backplane board has duplex-ready logic for switching the computer system between a SCSI simplex mode and a SCSI duplex mode. The duplex-ready logic includes a set of bus quick switches, a duplex-ready logic controller, and a set or sets of active terminators. The SCSI simplex mode and SCSI duplex mode are configured by the duplex-ready logic controller based on the number of SCSI cables present. If only a primary SCSI cable is present, the duplex-ready logic controller enables a SCSI simplex mode. To enable a SCSI simplex mode, the bus switches are enabled and the terminators are selectively enabled and/or disabled. If a primary SCSI cable and a secondary SCSI cable are present, the duplex-ready logic controller enables a SCSI duplex mode. To enable a SCSI duplex mode, the bus switches are disabled and the terminators are selectively disabled and/or enabled.
    Type: Grant
    Filed: January 16, 1998
    Date of Patent: April 25, 2000
    Assignee: Compaq Computer Corporation
    Inventors: Randall J. Pascarella, Vincent Nguyen