Abstract: An output driver circuit provides more constant slew rates in the presence of process, voltage, or temperature variations that affect performance. An open ended (no feedback) solution is utilized that provides more constant slew rates in spite of PVT variations. A first performance dependent current and a reference current are generated and a third current is generated that is inversely related to performance utilizing the reference current and the performance dependent current. The third current is supplied to a gate of a first transistor circuit forming a portion of the output driver to thereby control the slew rate.

Abstract: An integrated circuit includes a dual mode output driver configured for outputting an output signal according to either a high voltage mode or a low voltage mode, and a controller for controlling the dual mode output driver at the selected mode. The dual mode output driver includes a high-voltage pull-up/pull-down driver circuit and a low-voltage pull-up/pull-down driver circuit, the low-voltage pull-down transistor in series with the high-voltage pull-down transistor that is coupled to the output node. Protection circuitry prevents the low-voltage transistors from encountering an overvoltage condition during the high voltage mode, and controls the slew rate of the output signal during the low voltage mode.

Abstract: An output buffer having a controlled output slew rate comprises a first predriver circuit having a first RC circuit and a first output node and a second predriver circuit having a second RC circuit and a second output node. A buffer input node is coupled to the first and second predriver circuits. The output buffer further includes an output circuit having first and second input nodes and a third output node, where the first and second input nodes are coupled, respectively, to the first and second output nodes. The time constants of the RC circuits control a signal slew rate at the third output node of the output circuit, and the value of R may be selected to provide a predetermined, controlled slew rate range at the third output node. A selection circuit aids in the selection of an appropriate value for R.

Abstract: A random number generator generates high quality random numbers by sampling the output of a voltage controlled oscillator (VCO) at a frequency much lower than the frequency of the oscillator output. The output frequency of the oscillator is changed significantly during each sampling interval to help ensure the phase relationship of the VCO output and the sampling frequency is unpredictable. That may be accomplished by logically combing the sampling clock and an output from a linear feedback shift register in an exclusive OR gate and supplying that output as the most significant bit used to generate the voltage to control the oscillator. Additional outputs from the linear feedback shift register are also used to generate the control input to the VCO. A distilling circuit such as a CRC circuit or a linear feedback shift register shifts in successive output samples and generates a number therefrom to further increase the randomness of the generated random number.