Abstract: A method for fabricating a CMOS integrated circuit (IC) includes providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the semiconductor surface followed by forming at least a first metal including layer on the gate dielectric layer. A polysilicon or amorphous silicon layer is formed on the first metal including layer to form an intermediate gate electrode stack. A masking pattern is formed on the intermediate gate electrode stack. The polysilicon or amorphous silicon layer is dry etched using the masking pattern to define a patterned intermediate gate electrode stack over the NMOS or PMOS regions, wherein the dry etching stops on a portion of the first metal comprising layer. The masking pattern is removed using a first post etch clean for stripping the masking pattern.

Abstract: The present invention provides a process of manufacturing a semiconductor device that comprises a process of manufacturing a semiconductor device that includes plasma etching 250 through a patterned hardmask layer 210 located over a semiconductor substrate 225 wherein the plasma etching forms a modified layer 210a on the hardmask layer 210, and removing at least a substantial portion of the modified layer 210a by exposing the modified layer 210a to a post plasma clean process.