Patents by Inventor Randhir P. S. Thakur

Randhir P. S. Thakur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090056626
    Abstract: An apparatus for cyclical depositing of thin films on semiconductor substrates, comprising a process chamber having a gas distribution system with separate paths for process gases and an exhaust system synchronized with operation of valves dosing the process gases into a reaction region of the chamber.
    Type: Application
    Filed: October 30, 2008
    Publication date: March 5, 2009
    Inventors: RANDHIR P.S. THAKUR, Alfred W. Mak, Ming Xi, Walter Benjamin Glenn, Ahmad A. Khan, Ayad A. Al-Shaikh, Avgerinos V. Gelatos, Salvador P. Umotoy
  • Patent number: 7485961
    Abstract: A method is disclosed for reducing the effects of buckling, also referred to as cracking or wrinkling in multilayer heterostructures. The present method involves forming a planarization layer superjacent a semiconductor substrate. A barrier film having a structural integrity is formed superjacent the planarization layer. A second layer is formed superjacent the barrier film. The substrate is heated sufficiently to cause the planarization layer to expand according to a first thermal coefficient of expansion, the second layer to expand according to a second thermal coefficient of expansion, and the structural integrity of the barrier film to be maintained. This results in the barrier film isolating the planarization layer from the second layer, thereby preventing the planarization layer and the second layer from interacting during the heating step.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: February 3, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Trung T. Doan, Randhir P. S. Thakur, Yauh-Ching Liu
  • Publication number: 20080268617
    Abstract: Methods for cleaning substrate surfaces utilized in SOI technology are provided. In one embodiment, the method for cleaning substrate surfaces includes providing a first substrate and a second substrate, wherein the first substrate has a silicon oxide layer formed thereon and a cleavage plane defined therein, performing a wet cleaning process on the surfaces of the first substrate and the second substrate, and bonding the cleaned silicon oxide layer to the cleaned surface of the second substrate.
    Type: Application
    Filed: August 9, 2006
    Publication date: October 30, 2008
    Inventors: Randhir P. S. Thakur, Stephen Moffatt, Per-Ove Hansson, Steve Ghanayem
  • Patent number: 7432152
    Abstract: A polysilicon film is formed with enhanced selectivity by flowing chlorine during the formation of the film. The chlorine acts as an etchant to insulative areas adjacent polysilicon structures on which the film is desired to be formed. Bottom electrodes for capacitors are formed using this process, followed by an anneal to create hemishperical grain (HSG) polysilicon. Multilayer capacitor containers are formed in a non-oxidizing ambient so that no oxide is formed between the layers. The structure formed is planarized to form separate containers made from doped and undoped amorphous silicon layers. Selected ones of undoped layers are seeded in a chlorine containing environment and annealed to form HSG. A dielectric layer and second electrode are formed to complete the cell capacitor.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: October 7, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Randhir P. S. Thakur, James Pan
  • Publication number: 20080210671
    Abstract: A dynamic surface anneal apparatus for annealing a semiconductor workpiece has a workpiece support for supporting a workpiece, an optical source and scanning apparatus for scanning the optical source and the workpiece support relative to one another along a fast axis. The optical source includes an array of laser emitters arranged generally in successive rows of the emitters, the rows being transverse to the fast axis. Plural collimating lenslets overlie respective ones of the rows of emitters and provide collimation along the fast axis. The selected lenslets have one or a succession of optical deflection angles corresponding to beam deflections along the fast axis for respective rows of emitters. Optics focus light from the array of laser emitters onto a surface of the workpiece to form a succession of line beams transverse to the fast axis spaced along the fast axis in accordance with the succession of deflection angles.
    Type: Application
    Filed: August 23, 2006
    Publication date: September 4, 2008
    Inventors: Dean Jennings, Abhilash J. Mayur, Timothy N. Thomas, Vijay Parihar, Vedapuram S. Achutharaman, Randhir P. S. Thakur
  • Publication number: 20080038900
    Abstract: Methods for promoting interface bonding energy utilized in SOI technology are provided. In one embodiment, the method for promoting interface bonding energy includes providing a first substrate and a second substrate, wherein the first substrate has a silicon oxide layer formed thereon and a cleavage plane defined therein, performing a dry cleaning process on a surface of the silicon oxide layer and a surface of the second substrate, and bonding the cleaned silicon oxide surface of the first substrate to the cleaned surface of the second substrate.
    Type: Application
    Filed: August 9, 2006
    Publication date: February 14, 2008
    Inventors: Randhir P S Thakur, Stephen Moffatt, Per-Ove Hansson, Steve Ghanayem
  • Patent number: 7235498
    Abstract: This invention is embodied in an improved process for growing high-quality silicon dioxide layers on silicon by subjecting it to a gaseous mixture of nitrous oxide (N2O) and ozone (O3). The presence of O3 in the oxidizing ambiance greatly enhances the oxidation rate compared to an ambiance in which N2O is the only oxidizing agent. In addition to enhancing the oxidation rate of silicon, it is hypothesized that the presence of O3 interferes with the growth of a thin silicon oxynitride layer near the interface of the silicon dioxide layer and the unreacted silicon surface which makes oxidation in the presence of N2O alone virtually self-limiting. The presence of O3 in the oxidizing ambiance does not impair oxide reliability, as is the case when silicon is oxidized with N2O in the presence of a strong, fluorine-containing oxidizing agent such as NF3 or SF6.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: June 26, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Singh Sandhu, Randhir P S Thakur
  • Patent number: 7232728
    Abstract: This invention improves the quality of gate oxide dielectric layers using a two-pronged approach, thus permitting the use of much thinner silicon dioxide gate dielectric layers required for lower-voltage, ultra-dense integrated circuits. In order to eliminate defects caused by imperfections in bulk silicon, an in-situ grown epitaxial layer is formed on active areas following a strip of the pad oxide layer used beneath the silicon nitride islands used for masking during the field oxidation process. By growing an epitaxial silicon layer prior to gate dielectric layer formation, defects in the bulk silicon substrate are covered over and, hence, isolated from the oxide growth step. In order to maintain the integrity of the selective epitaxial growth step, the wafers are maintained in a controlled, oxygen-free environment until the epitaxial growth step is accomplished.
    Type: Grant
    Filed: January 30, 1996
    Date of Patent: June 19, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Ruojia R. Lee, Randhir P. S. Thakur
  • Patent number: 7229890
    Abstract: A polysilicon film is formed with enhanced selectivity by flowing chlorine during the formation of the film. The chlorine acts as an etchant to insulative areas adjacent polysilicon structures on which the film is desired to be formed. Bottom electrodes for capacitors are formed using this process, followed by an anneal to create hemishperical grain (HSG) polysilicon. Multilayer capacitor containers are formed in a non-oxidizing ambient so that no oxide is formed between the layers. The structure formed is planarized to form separate containers made from doped and undoped amorphous silicon layers. Selected ones of undoped layers are seeded in a chlorine containing environment and annealed to form HSG. A dielectric layer and second electrode are formed to complete the cell capacitor.
    Type: Grant
    Filed: February 18, 2003
    Date of Patent: June 12, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Randhir P. S. Thakur, James Pan
  • Patent number: 7217614
    Abstract: A first electrode and a doped oxide layer laterally proximate thereof are provided over a substrate. A silicon nitride layer is formed over both the doped oxide layer and the first electrode to a thickness of no greater than 80 Angstroms over at least the first electrode by low pressure chemical vapor deposition using feed gases comprising a silicon hydride, H2 and ammonia. The substrate with silicon nitride layer is exposed to oxidizing conditions comprising at least 700° C. to form a silicon dioxide layer over the silicon nitride layer, with the thickness of silicon nitride over the doped oxide layer being sufficient to shield oxidizable substrate material beneath the doped oxide layer from oxidizing during the exposing. A second electrode is formed over the silicon dioxide layer and the first electrode. In one implementation, the chemical vapor depositing comprises feed gases of a silicon hydride and ammonia, with the depositing comprising increasing internal reactor temperature from below 500° C.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: May 15, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Randhir P.S. Thakur
  • Patent number: 7205600
    Abstract: A capacitor forming method can include forming an insulation layer over a substrate and forming a barrier layer to threshold voltage shift inducing material over the substrate. An opening can be formed at least into the insulation layer and a capacitor dielectric layer formed at least within the opening. Threshold voltage inducing material can be provided over the barrier layer but be retarded in movement into an electronic device comprised by the substrate. The dielectric layer can comprise a tantalum oxide and the barrier layer can include a silicon nitride. Providing threshold voltage shift inducing material can include oxide annealing dielectric layer such as with N2O. The barrier layer can be formed over the insulation layer, the insulation layer can be formed over the barrier layer, or the barrier layer can be formed over a first insulation layer with a second insulation layer formed over the barrier layer.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: April 17, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Vishnu K. Agarwal, F. Daniel Gealy, Kunal R. Parekh, Randhir P. S. Thakur
  • Patent number: 7206215
    Abstract: A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film. Embodiments include a method of operating an antifuse, comprising applying a voltage across electrodes of a capacitor having a tantalum oxynitride film and forming a hole in the tantalum oxynitride film.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: April 17, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Scott Jeffrey DeBoer, Husam N. Al-Shareef, Randhir P. S. Thakur, Dan Gealy
  • Patent number: 7192889
    Abstract: A method of forming a high dielectric oxide film conventionally formed using a post formation oxygen anneal to reduce the leakage current of such film includes forming a high dielectric oxide film on a surface. The high dielectric oxide film has a dielectric constant greater than about 4 and includes a plurality of oxygen vacancies present during the formation of the film. The high dielectric oxide film is exposed during the formation thereof to an amount of atomic oxygen sufficient for reducing the number of oxygen vacancies and eliminating the post formation oxygen anneal of the high dielectric oxide film. Further, the amount of atomic oxygen used in the formation method may be controlled as a function of the amount of oxygen incorporated into the high dielectric oxide film during the formation thereof or be controlled as a function of the concentration of atomic oxygen in a process chamber in which the high dielectric oxide film is being formed.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: March 20, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. DeBoer, Randhir P. S. Thakur
  • Patent number: 7175713
    Abstract: An apparatus for cyclical depositing of thin films on semiconductor substrates, comprising a process chamber having a gas distribution system with separate paths for process gases and an exhaust system synchronized with operation of valves dosing the process gases into a reaction region of the chamber.
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: February 13, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Randhir P. S. Thakur, Alfred W. Mak, Ming Xi, Walter Benjamin Glenn, Ahmad A. Khan, Ayad A. Al-Shaikh, Avgerinos V. Gelatos, Salvador P. Umotoy
  • Patent number: 7101756
    Abstract: Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: September 5, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Randhir P. S. Thakur, Garry A. Mercaldi, Michael Nuttall, Shenlin Chen, Er-Xuan Ping
  • Patent number: 7067442
    Abstract: A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: June 27, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Randhir P. S. Thakur, Ravi Iyer, Howard Rhodes
  • Patent number: 7067411
    Abstract: A selective spacer to prevent metal oxide formation during polycide reoxidation of a feature such as an electrode and a method for forming the selective spacer are disclosed. A material such as a thin silicon nitride or an amorphous silicon film is selectively deposited on the electrode by limiting deposition time to a period less than an incubation time for the material on silicon dioxide near the electrode. The spacer is deposited only on the electrode and not on surrounding silicon dioxide. The spacer serves as a barrier for the electrode during subsequent oxidation to prevent metal oxide formation while allowing oxidation to take place over the silicon dioxide.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: June 27, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Klaus Florian Schuegraf, Scott Jeffrey DeBoer, Randhir P. S. Thakur
  • Patent number: 7038265
    Abstract: A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: May 2, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Scott Jeffrey DeBoer, Husam N. Al-Shareef, Randhir P. S. Thakur, Dan Gealy
  • Patent number: 7034353
    Abstract: Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: April 25, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Randhir P. S. Thakur, Garry A. Mercaldi, Michael Nuttall, Shenlin Chen, Er-Xuan Ping
  • Patent number: 7009264
    Abstract: A selective spacer to prevent metal oxide formation during polycide reoxidation of a feature such as an electrode and a method for forming the selective spacer are disclosed. A material such as a thin silicon nitride or an amorphous silicon film is selectively deposited on the electrode by limiting deposition time to a period less than an incubation time for the material on silicon dioxide near the electrode. The spacer is deposited only on the electrode and not on surrounding silicon dioxide. The spacer serves as a barrier for the electrode during subsequent oxidation to prevent metal oxide formation while allowing oxidation to take place over the silicon dioxide.
    Type: Grant
    Filed: July 30, 1997
    Date of Patent: March 7, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Klaus Florian Schuegraf, Scott Jeffrey DeBoer, Randhir P. S. Thakur