Patents by Inventor Randhir S. Bubber
Randhir S. Bubber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7037574Abstract: An atomic layer deposition (ALD) process deposits thin films for microelectronic structures, such as advanced gap and tunnel junction applications, by plasma annealing at varying film thicknesses to obtain desired intrinsic film stress and breakdown film strength. The primary advantage of the ALD process is the near 100% step coverage with properties that are uniform along sidewalls. The process provides smooth (Ra˜2 ?), pure (impurities<1 at. %), AlOx films with improved breakdown strength (9–10 MV/cm) with a commercially feasible throughput.Type: GrantFiled: May 23, 2001Date of Patent: May 2, 2006Assignee: Veeco Instruments, Inc.Inventors: Ajit P. Paranjpe, Sanjay Gopinath, Thomas R. Omstead, Randhir S. Bubber, Ming Mao
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Patent number: 6812126Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier comprises a dopant selected from the group consisting of platinum, palladium, iridium, rhodium, and time. The barrier can comprises a refractory metal selected from the group consisting of tantalum, tungsten titanium, chromium, and cobalt, and can also comprise a third element selected from the group consisting of carbon, oxygen and nitrogen. The dopant and other barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.Type: GrantFiled: April 21, 2000Date of Patent: November 2, 2004Assignee: CVC Products, Inc.Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Randhir S. Bubber, Lino A. Velo
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Patent number: 6645847Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.Type: GrantFiled: January 30, 2002Date of Patent: November 11, 2003Assignee: CVC Products, Inc.Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Boris Relja, Randhir S. Bubber, Lino A. Velo, Thomas R. Omstead, David R. Campbell, Sr., David M. Leet, Sanjay Gopinath
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Patent number: 6627995Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.Type: GrantFiled: April 1, 2002Date of Patent: September 30, 2003Assignee: CVC Products, Inc.Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Boris Relja, Randhir S. Bubber, Lino A. Velo, Thomas R. Omstead, David R. Campbell, Sr., David M. Leet, Sanjay Gopinath
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Publication number: 20030003635Abstract: An atomic layer deposition (ALD) process deposits thin films for microelectronic structures, such as advanced gap and tunnel junction applications, by plasma annealing at varying film thicknesses to obtain desired intrinsic film stress and breakdown film strength. The primary advantage of the ALD process is the near 100% step coverage with properties that are uniform along sidewalls. The process provides smooth (Ra˜2 Å), pure (impurities <1 at. %), AlOx films with improved breakdown strength (9-10 MV/cm) with a commercially feasible throughput.Type: ApplicationFiled: May 23, 2001Publication date: January 2, 2003Inventors: Ajit P. Paranjpe, Sanjay Gopinath, Thomas R. Omstead, Randhir S. Bubber, Ming Mao
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Publication number: 20020137332Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.Type: ApplicationFiled: April 1, 2002Publication date: September 26, 2002Applicant: CVC Products, Inc., a Delware corporationInventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Boris Relja, Randhir S. Bubber, Lino A. Velo, Thomas R. Omstead, David R. Campbell, David M. Leet, Sanjay Gopinath
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Patent number: 6444263Abstract: A method for chemical-vapor deposition of a material film adds precursor decomposition by-product to the precursor flow to suppress premature gas-phase precursor decomposition and improve process repeatability and film quality. In one embodiment, CVD cobalt films are deposited with carbonyl precursors with reduced premature gas-phase reaction and particulate generation by the addition of excess carbon monoxide to the process chamber comprising the precursor flow. The addition of carbon monoxide not only suppresses gas-phase reaction but also improves cobalt film purity. The addition of excess carbon monoxide to CVD cobalt precursor flow provides repeatable deposition of glue and nucleation layers to support CVD copper, and is extendable to the deposition of high purity CVD cobalt for other applications and with other precursors, and also extendable for CVD CoSi2 films and other cobalt-containing applications.Type: GrantFiled: September 15, 2000Date of Patent: September 3, 2002Assignee: CVC Products, Inc.Inventors: Ajit P. Paranjpe, Randhir S. Bubber, Sanjay Gopinath, Thomas R. Omstead, Mehrdad M. Moslehi
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Publication number: 20020102838Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.Type: ApplicationFiled: January 30, 2002Publication date: August 1, 2002Applicant: CVC Products, Inc., a Delaware corporationInventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Boris Relja, Randhir S. Bubber, Lino A. Velo, Thomas R. Omstead, David R. Campbell, David M. Leet, Sanjay Gopinath
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Patent number: 6365502Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.Type: GrantFiled: March 3, 2000Date of Patent: April 2, 2002Assignee: CVC Products, Inc.Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Boris Relja, Randhir S. Bubber, Lino A. Velo, Thomas R. Omstead, David R. Campbell, Sr., David M. Leet, Sanjay Gopinath
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Patent number: 6294836Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier comprises a dopant selected from the group consisting of platinum, palladium, iridium, rhodium, and tin. The barrier can comprise a refractory metal selected from the group consisting of tantalum, tungsten titanium, chromium, and cobalt, and can also comprise a third element selected from the group consisting of carbon, oxygen and nitrogen. The dopant and other barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization in one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.Type: GrantFiled: December 22, 1998Date of Patent: September 25, 2001Assignee: CVC Products Inc.Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Randhir S. Bubber, Lino A. Velo
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Patent number: 6204204Abstract: A method and apparatus are disclosed for depositing a tantalum-containing diffusion barrier, such as a TaN barrier layer, by dissolving a tantalum-bearing organometallic precursor, such as PEMAT or PDEAT, in an inert, low viscosity, high molecular weight, low volatility solvent, such as octane, heptane, decane or toluene. The precursor-solvent solution is vaporized and flowed over a substrate to deposit the barrier. The precursor solution has a viscosity substantially similar to that of the solvent by maintaining the ratio of precursor to solvent at a generally low value, such as approximately 10% precursor. The boiling point of the solvent is substantially similar to the boiling point of the precursor, such as within 50% of the precursor boiling point at one atmosphere, to enhance repeatability of barrier film quality.Type: GrantFiled: April 1, 1999Date of Patent: March 20, 2001Assignee: CVC Products, Inc.Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Randhir S. Bubber, Lino A. Velo