Patents by Inventor Randhir Thakur
Randhir Thakur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9991134Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.Type: GrantFiled: April 7, 2014Date of Patent: June 5, 2018Assignee: Applied Materials, Inc.Inventors: Anchuan Wang, Xinglong Chen, Zihui Li, Hiroshi Hamana, Zhijun Chen, Ching-Mei Hsu, Jiayin Huang, Nitin K. Ingle, Dmitry Lubomirsky, Shankar Venkataraman, Randhir Thakur
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Patent number: 9812328Abstract: Embodiments described herein generally relate to methods for forming silicide materials. Silicide materials formed according to the embodiments described herein may be utilized as contact and/or interconnect structures and may provide advantages over conventional silicide formation methods. In one embodiment, a one or more transition metal and aluminum layers may be deposited on a silicon containing substrate and a transition metal layer may be deposited on the one or more transition metal and aluminum layers. An annealing process may be performed to form a metal silicide material.Type: GrantFiled: June 22, 2016Date of Patent: November 7, 2017Assignee: APPLIED MATERIALS, INC.Inventors: Kaushal K. Singh, Er-Xuan Ping, Xianmin Tang, Sundar Ramamurthy, Randhir Thakur
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Patent number: 9773695Abstract: Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called “2-d flat cell” flash architectures. 2-d flat cell flash memory involves a reactive ion etch to dig trenches into multi-layers containing high work function and other metal layers. The methods described herein remove the metal oxide debris from the sidewalls of the multi-layer trench and then, without breaking vacuum, selectively remove shallow trench isolation (STI) oxidation which become the air gaps. Both the metal oxide removal and the STI oxidation removal are carried out in the same mainframe with highly selective etch processes using remotely excited fluorine plasma effluents.Type: GrantFiled: October 24, 2016Date of Patent: September 26, 2017Assignee: Applied Materials, Inc.Inventors: Vinod R. Purayath, Randhir Thakur, Shankar Venkataraman, Nitin K. Ingle
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Patent number: 9704723Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.Type: GrantFiled: November 9, 2015Date of Patent: July 11, 2017Assignee: Applied Materials, Inc.Inventors: Anchuan Wang, Xinglong Chen, Zihui Li, Hiroshi Hamana, Zhijun Chen, Ching-Mei Hsu, Jiayin Huang, Nitin K. Ingle, Dmitry Lubomirsky, Shankar Venkataraman, Randhir Thakur
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Patent number: 9659792Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.Type: GrantFiled: July 24, 2015Date of Patent: May 23, 2017Assignee: Applied Materials, Inc.Inventors: Anchuan Wang, Xinglong Chen, Zihui Li, Hiroshi Hamana, Zhijun Chen, Ching-Mei Hsu, Jiayin Huang, Nitin K. Ingle, Dmitry Lubomirsky, Shankar Venkataraman, Randhir Thakur
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Publication number: 20170040207Abstract: Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called “2-d flat cell” flash architectures. 2-d flat cell flash memory involves a reactive ion etch to dig trenches into multi-layers containing high work function and other metal layers. The methods described herein remove the metal oxide debris from the sidewalls of the multi-layer trench and then, without breaking vacuum, selectively remove shallow trench isolation (STI) oxidation which become the air gaps. Both the metal oxide removal and the STI oxidation removal are carried out in the same mainframe with highly selective etch processes using remotely excited fluorine plasma effluents.Type: ApplicationFiled: October 24, 2016Publication date: February 9, 2017Applicant: Applied Materials, Inc.Inventors: Vinod R. Purayath, Randhir Thakur, Shankar Venkataraman, Nitin K. Ingle
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Publication number: 20160372371Abstract: Embodiments described herein generally relate to methods for forming silicide materials. Silicide materials formed according to the embodiments described herein may be utilized as contact and/or interconnect structures and may provide advantages over conventional silicide formation methods. In one embodiment, a one or more transition metal and aluminum layers may be deposited on a silicon containing substrate and a transition metal layer may be deposited on the one or more transition metal and aluminum layers. An annealing process may be performed to form a metal silicide material.Type: ApplicationFiled: June 22, 2016Publication date: December 22, 2016Inventors: Kaushal K. SINGH, Er-Xuan PING, Xianmin TANG, Sundar RAMAMURTHY, Randhir THAKUR
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Patent number: 9496167Abstract: Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called “2-d flat cell” flash architectures. 2-d flat cell flash memory involves a reactive ion etch to dig trenches into multi-layers containing high work function and other metal layers. The methods described herein remove the metal oxide debris from the sidewalls of the multi-layer trench and then, without breaking vacuum, selectively remove shallow trench isolation (STI) oxidation which become the air gaps. Both the metal oxide removal and the STI oxidation removal are carried out in the same mainframe with highly selective etch processes using remotely excited fluorine plasma effluents.Type: GrantFiled: July 31, 2014Date of Patent: November 15, 2016Assignee: Applied Materials, Inc.Inventors: Vinod R. Purayath, Randhir Thakur, Shankar Venkataraman, Nitin K. Ingle
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Patent number: 9449850Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.Type: GrantFiled: May 4, 2015Date of Patent: September 20, 2016Assignee: Applied Materials, Inc.Inventors: Anchuan Wang, Xinglong Chen, Zihui Li, Hiroshi Hamana, Zhijun Chen, Ching-Mei Hsu, Jiayin Huang, Nitin K. Ingle, Dmitry Lubomirsky, Shankar Venkataraman, Randhir Thakur
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Patent number: 9431267Abstract: In some embodiments, an electronic device processing system is provided that includes a processing tool having a first subsystem configured to carry out a first subset of processes on a substrate having pattern features, the first subsystem including a first conformal deposition chamber and a first etch chamber. The processing tool includes a second subsystem coupled to the first subsystem and configured to carry out a second subset of processes on the substrate, the second subsystem including a second conformal deposition chamber and a second etch chamber. The processing tool is configured to employ the first and second subsystems to perform pitch division on the substrate within the processing tool so as to form a reduced-pitch pattern on the substrate. Numerous other embodiments are provided.Type: GrantFiled: December 1, 2013Date of Patent: August 30, 2016Assignee: Applied Materials, Inc.Inventors: Mayur Trivedi, Sushil Padiyar, Lakshmanan Karuppiah, Randhir Thakur
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Patent number: 9378978Abstract: Methods of etching back shallow trench isolation (STI) dielectric and trimming the exposed floating gate without breaking vacuum are described. The methods include recessing silicon oxide dielectric gapfill to expose vertical sidewalls of polysilicon floating gates. The exposed vertical sidewalls are then isotropically etched to evenly thin the polysilicon floating gates on the same substrate processing mainframe. Both recessing silicon oxide and isotropically etching polysilicon use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. An inter-poly dielectric may then be conformally deposited either on the same mainframe or outside the mainframe.Type: GrantFiled: July 31, 2014Date of Patent: June 28, 2016Assignee: Applied Materials, Inc.Inventors: Vinod R. Purayath, Randhir Thakur, Shankar Venkataraman, Nitin K. Ingle
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Publication number: 20160064233Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.Type: ApplicationFiled: November 9, 2015Publication date: March 3, 2016Inventors: Anchuan Wang, Xinglong Chen, Zihui Li, Hiroshi Hamana, Zhijun Chen, Ching-Mei Hsu, Jiayin Huang, Nitin K. Ingle, Dmitry Lubomirsky, Shankar Venkataraman, Randhir Thakur
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Publication number: 20160042968Abstract: Methods of forming single crystal channel material in a 3-d flash memory cell using only gas-phase etching techniques are described. The methods include gas-phase etching native oxide from a polysilicon layer on a conformal ONO layer. The gas-phase etch also removes native oxide from the exposed single crystal silicon substrate the bottom of a 3-d flash memory hole. The polysilicon layer is removed, also with a gas-phase etch, on the same substrate processing mainframe. Both native oxide removal and polysilicon removal use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. Epitaxial silicon is then grown from the exposed single crystal silicon to create a high mobility replacement channel.Type: ApplicationFiled: August 5, 2014Publication date: February 11, 2016Inventors: Vinod R. Purayath, Randhir Thakur, Nitin K. Ingle
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Publication number: 20160043099Abstract: Methods of forming air gaps in a 3-d flash memory cell using only gas-phase etching techniques are described. The methods include selectively gas-phase etching tungsten deposited into the stack structure to separate the tungsten levels. Other metals than tungsten may be used. The methods also include selectively etching silicon oxide from between the tungsten levels to make room for vertically spaced air gaps. A nonconformal silicon oxide layer is then deposited to trap the air gaps. Both tungsten removal and silicon oxide removal use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. The nonconformal silicon oxide may be deposited inside or outside the mainframe.Type: ApplicationFiled: August 5, 2014Publication date: February 11, 2016Inventors: Vinod R. Purayath, Randhir Thakur, Shankar Venkataraman, Nitin K. Ingle
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Publication number: 20160035586Abstract: Methods of etching back shallow trench isolation (STI) dielectric and trimming the exposed floating gate without breaking vacuum are described. The methods include recessing silicon oxide dielectric gapfill to expose vertical sidewalls of polysilicon floating gates. The exposed vertical sidewalls are then isotropically etched to evenly thin the polysilicon floating gates on the same substrate processing mainframe. Both recessing silicon oxide and isotropically etching polysilicon use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. An inter-poly dielectric may then be conformally deposited either on the same mainframe or outside the mainframe.Type: ApplicationFiled: July 31, 2014Publication date: February 4, 2016Inventors: Vinod R. Purayath, Randhir Thakur, Shankar Venkataraman, Nitin K. Ingle
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Publication number: 20160035614Abstract: Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called “2-d flat cell” flash architectures. 2-d flat cell flash memory involves a reactive ion etch to dig trenches into multi-layers containing high work function and other metal layers. The methods described herein remove the metal oxide debris from the sidewalls of the multi-layer trench and then, without breaking vacuum, selectively remove shallow trench isolation (STI) oxidation which become the air gaps. Both the metal oxide removal and the STI oxidation removal are carried out in the same mainframe with highly selective etch processes using remotely excited fluorine plasma effluents.Type: ApplicationFiled: July 31, 2014Publication date: February 4, 2016Inventors: Vinod R. Purayath, Randhir Thakur, Shankar Venkataraman, Nitin K. Ingle
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Publication number: 20160027673Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.Type: ApplicationFiled: October 5, 2015Publication date: January 28, 2016Inventors: Anchuan Wang, Xinglong Chen, Zihui Li, Hiroshi Hamana, Zhijun Chen, Ching-Mei Hsu, Jiayin Huang, Nitin K. Ingle, Dmitry Lubomirsky, Shankar Venkataraman, Randhir Thakur
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Publication number: 20150332930Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.Type: ApplicationFiled: July 24, 2015Publication date: November 19, 2015Inventors: Anchuan Wang, Xinglong Chen, Zihui Li, Hiroshi Hamana, Zhijun Chen, Ching-Mei Hsu, Jiayin Huang, Nitin K. Ingle, Dmitry Lubomirsky, Shankar Venkataraman, Randhir Thakur
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Patent number: 9184055Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.Type: GrantFiled: April 7, 2014Date of Patent: November 10, 2015Assignee: Applied Materials, Inc.Inventors: Anchuan Wang, Xinglong Chen, Zihui Li, Hiroshi Hamana, Zhijun Chen, Ching-Mei Hsu, Jiayin Huang, Nitin K. Ingle, Dmitry Lubomirsky, Shankar Venkataraman, Randhir Thakur
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Patent number: 9165786Abstract: Methods of etching back an oxide-nitride-oxide (ONO) layer of a 3-d flash memory cell without breaking vacuum are described. The methods include recessing the two outer silicon oxide dielectric layers to expose the flanks of the thin silicon nitride layer. The silicon nitride layer is then etched back from all exposed sides to hasten the process on the same substrate processing mainframe. Both etching back the silicon oxide and etching back the silicon nitride use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. The process may also be reversed such that the silicon nitride is etched back first.Type: GrantFiled: August 5, 2014Date of Patent: October 20, 2015Assignee: Applied Materials, Inc.Inventors: Vinod R. Purayath, Randhir Thakur, Nitin K. Ingle