Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: A plurality of temperature dependent focal plane arrays operate without a temperature stabilization cooler and/or heater over a wide range of ambient temperatures. Gain, offset and/or bias correction tables are provided in a flash memory in memory pages indexed by the measured temperature of the focal plane arrays. The memory stores a calibration database, which is accessed using a logic circuit which generates a memory page address from a digitized temperature measurement of each of the focal plane array. The calibration database is comprised of an array of bias, gain and offset values for each pixel in the focal plane array for each potential operating temperature over the entire range of potential operating temperatures. The bias, gain and offset data within the database are read out, converted to analog form, and used by analog circuits to correct the focal plane array response.

Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.