Patents by Inventor Randolph Knarr
Randolph Knarr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10541141Abstract: A method for selectively etching an etch layer with respect to a mask is provided. An etch process is provided comprising a plurality of etch cycles, wherein each etch cycle comprises providing a deposition phase and an etch phase. The deposition phase comprises providing a flow of a deposition phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio, providing a RF power, which forms the deposition phase gas into a plasma, and stopping the deposition phase. The etch phase, comprises providing a flow of an etch phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio that is lower than the fluorocarbon or hydrofluorocarbon to oxygen ratio of the deposition phase gas, providing a RF power, and stopping the etch phase.Type: GrantFiled: July 25, 2018Date of Patent: January 21, 2020Assignee: Lam Research CorporationInventors: Adarsh Basavalingappa, Peng Wang, Bhaskar Nagabhirava, Michael Goss, Prabhakara Gopaladasu, Randolph Knarr, Stefan Schmitz, Phil Friddle
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Publication number: 20180330959Abstract: A method for selectively etching an etch layer with respect to a mask is provided. An etch process is provided comprising a plurality of etch cycles, wherein each etch cycle comprises providing a deposition phase and an etch phase. The deposition phase comprises providing a flow of a deposition phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio, providing a RF power, which forms the deposition phase gas into a plasma, and stopping the deposition phase. The etch phase, comprises providing a flow of an etch phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio that is lower than the fluorocarbon or hydrofluorocarbon to oxygen ratio of the deposition phase gas, providing a RF power, and stopping the etch phase.Type: ApplicationFiled: July 25, 2018Publication date: November 15, 2018Inventors: Adarsh BASAVALINGAPPA, Peng WANG, Bhaskar NAGABHIRAVA, Michael GOSS, Prabhakara GOPALADASU, Randolph KNARR, Stefan SCHMITZ, Phil FRIDDLE
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Patent number: 10037890Abstract: A method for selectively etching an etch layer with respect to a mask is provided. An etch process is provided comprising a plurality of etch cycles, wherein each etch cycle comprises providing a deposition phase and an etch phase. The deposition phase comprises providing a flow of a deposition phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio, providing a RF power, which forms the deposition phase gas into a plasma, and stopping the deposition phase. The etch phase, comprises providing a flow of an etch phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio that is lower than the fluorocarbon or hydrofluorocarbon to oxygen ratio of the deposition phase gas, providing a RF power, and stopping the etch phase.Type: GrantFiled: October 11, 2016Date of Patent: July 31, 2018Assignee: Lam Research CorporationInventors: Adarsh Basavalingappa, Peng Wang, Bhaskar Nagabhirava, Michael Goss, Prabhakara Gopaladasu, Randolph Knarr, Stefan Schmitz, Phil Friddle
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Publication number: 20180102253Abstract: A method for selectively etching an etch layer with respect to a mask is provided. An etch process is provided comprising a plurality of etch cycles, wherein each etch cycle comprises providing a deposition phase and an etch phase. The deposition phase comprises providing a flow of a deposition phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio, providing a RF power, which forms the deposition phase gas into a plasma, and stopping the deposition phase. The etch phase, comprises providing a flow of an etch phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio that is lower than the fluorocarbon or hydrofluorocarbon to oxygen ratio of the deposition phase gas, providing a RF power, and stopping the etch phase.Type: ApplicationFiled: October 11, 2016Publication date: April 12, 2018Inventors: Adarsh BASAVALINGAPPA, Peng WANG, Bhaskar NAGABHIRAVA, Michael GOSS, Prabhakara GOPALADASU, Randolph KNARR, Stefan SCHMITZ, Phil FRIDDLE
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Publication number: 20160343806Abstract: Methods for fabricating interface passivation layers in a circuit structure are provided. The method includes forming a silicon-germanium layer over a substrate, removing a native oxide layer from an upper surface of the silicon-germanium layer, and exposing the upper surface of the silicon-germanium layer to an ozone-containing solution, resulting in an interface passivation layer with a higher concentration of germanium-dioxide present than germanium-oxide. The resulting interface passivation layer may be part of a gate structure, in which the channel region of the gate structure includes the silicon-germanium layer and the interface passivation layer between the channel region and the dielectric layer of the gate structure has a high concentration of germanium-dioxide.Type: ApplicationFiled: May 21, 2015Publication date: November 24, 2016Applicants: GLOBALFOUNDRIES INC., LAM RESEARCH CORPORATION, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shariq SIDDIQUI, Jody A. FRONHEISER, Murat Kerem AKARVARDAR, Purushothaman SRINIVASAN, Lisa F. EDGE, Gangadhara Raja MUTHINTI, Georges JACOBI, Randolph KNARR
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Publication number: 20070254479Abstract: The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.Type: ApplicationFiled: May 1, 2006Publication date: November 1, 2007Applicant: International Business Machines CorporationInventors: Sunfei Fang, Randolph Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Renee Mo, Balasubramanian Pranatharthiharan, Jay Strane
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Publication number: 20070222066Abstract: A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric.Type: ApplicationFiled: March 24, 2006Publication date: September 27, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, Hariklia Deligianni, Randolph Knarr, Sandra Malhotra, Stephen Rossnagel, Xiaoyan Shao, Anna Topol, Philippe Vereecken
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Publication number: 20060081981Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.Type: ApplicationFiled: November 10, 2005Publication date: April 20, 2006Applicant: International Business Machines CorporationInventors: Julie Biggs, Tien-Jen Cheng, David Eichstadt, Lisa Fanti, Jonathan Griffith, Randolph Knarr, Sarah Knickerbocker, Kevin Petrarca, Roger Quon, Wolfgang Sauter, Kamalesh Srivastava, Richard Volant
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Publication number: 20060051961Abstract: The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step. A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.Type: ApplicationFiled: September 7, 2004Publication date: March 9, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, Michael Cobb, Balasubramanian Pranatharthi Haran, Randolph Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Andrew Mansson, Horatio Wildman
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Publication number: 20050245070Abstract: A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the multi-layered barrier in a recess of the device terminal by use of a single electroplating chemistry to enhance protection against voiding and de-lamination due to the diffusion of copper, whether by self-diffusion or electro-migration. The barrier includes at least a first layer of nickel-rich material and a second layer of copper-rich material. The barrier enables use of higher current densities for advanced complementary metal-oxide semiconductors (CMOS) designs, and extends the reliability of current CMOS designs regardless of solder selection. Moreover, this technology is easily adapted to current methods of fabricating electroplated interconnects such as C4s.Type: ApplicationFiled: April 28, 2004Publication date: November 3, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Panayotis Andricacos, Tien-Jen Cheng, Emanuel Cooper, David Eichstadt, Jonathan Griffith, Randolph Knarr, Roger Quon, Erik Roggeman
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Publication number: 20050062170Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.Type: ApplicationFiled: September 18, 2003Publication date: March 24, 2005Applicant: International Business Machines CorporationInventors: Julie Biggs, Tien-Jen Cheng, David Eichstadt, Lisa Fanti, Jonathan Griffith, Randolph Knarr, Sarah Knickerbocker, Kevin Petrarca, Roger Quon, Wolfgang Sauter, Kamalesh Srivastava, Richard Volant
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Publication number: 20050026416Abstract: A solder bump for bonding an electronic device to a substrate or another structure is formed by plating a high aspect ratio copper pin on a supporting structure, encapsulating the pin in a barrier material, plating a solder on the barrier material and then reflowing the solder.Type: ApplicationFiled: July 31, 2003Publication date: February 3, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tien-Jen Cheng, David Eichstadt, Jonathan Griffith, Randolph Knarr, Kevin Petrarca, Roger Quon