Abstract: A processor for operating on video and azimuth signals from a radar system having an antenna which scans in azimuth. The processor enhances the signal-to-noise ratio of the video signals while imposing thereon a substantially constant azimuth delay error.The processor includes a first circuit for forming and storing a count indicative of the video signal history in each range zone. The processor also includes a second circuit for generating and removing a flag signal indicative of azimuth leading and trailing edges respectively of a target pulse in the video signal. A gating circuit is included to pass video signals, for a given range zone, to an output terminal during the presence of a flag signal associated with the zone.