Abstract: Generating a still image from a sequence of video frames comprises the steps of receiving a sequence of video frames and storing a predetermined number of the sequence of video frames temporally adjacent to an user initiated capture event, the predetermined number of frames being defined as a cliplet. Video capture is performed using cliplets, which are short video segments, preferably in compressed data format. A crop-and-process instruction is added to the cliplet. All processing, handling or storage of the data is cliplet based. Editing instructions are stored with the cliplet allowing editing to be performed by a user at one resolution and then re-performed at a higher resolution at a server where it is printed. Modified reprints of an image can be obtained without resending the images and adequate storage for the cliplets can be assured. Encryption of the cliplets during transmission and storage is facilitated by cliplet-based processing.

Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m*N where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m*N where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: A chip stack includes a field programmable gate array (FPGA) and an auxiliary component coupled to the FPGA with intercommunicated clock, control and/or data signals. The auxiliary component has a functionality mapped into the FPGA. The pin definition of the FPGA is redefined so that the FPGA and the auxiliary component in combination operate as a modified FPGA. A test circuit is programmed into the FPGA to exercise the auxiliary component to test functionality and timing performance at full speed. The functionality of the auxiliary component mapped into the FPGA is parameterized, such as for the data word width for reading and/or writing data words of different lengths into the auxiliary component in both an aligned and nonaligned manner. A memory interface allows multiple auxiliary circuits to be accessed through the FPGA either together to generate a wider data word or serially to achieve a greater memory depth.

Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as mXN where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m×N where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: A method of processing low resolution input frames containing undersampled views of an optically imaged scene to produce a higher quality, higher resolution output frame. This method operates by obtaining a sequence of low resolution input frames containing different undersampled views of an optically imaged scene.

Abstract: Generating a still image from a sequence of video frames comprises the steps of receiving a sequence of video frames and storing a predetermined number of the sequence of video frames temporally adjacent to an user initiated capture event, the predetermined number of frames being defined as a cliplet. Video capture is performed using cliplets, which are short video segments, preferably in compressed data format. A crop-and-process instruction is added to the cliplet. All processing, handling or storage of the data is cliplet based. Editing instructions are stored with the cliplet allowing editing to be performed by a user at one resolution and then re-performed at a higher resolution at a server where it is printed. Modified reprints of an image can be obtained without resending the images and adequate storage for the cliplets can be assured. Encryption of the cliplets during transmission and storage is facilitated by cliplet-based processing.

Abstract: A temperature dependent focal plane array operates without a temperature stabilization cooler and/or heater over a wide range of ambient temperatures. Gain, offset and/or bias correction tables are provided in a flash memory in memory pages indexed by the measured temperature of the focal plane array. The memory stores a calibration database, which is accessed using a logic circuit which generates a memory page address from a digitized temperature measurement of the focal plane array. The calibration database is comprised of an array of bias, gain and offset values for each pixel in the focal plane array for each potential operating temperature over the entire range of potential operating temperatures. The bias, gain and offset data within the database are read out, converted to analog form, and used by analog circuits to correct the focal plane array response.

Abstract: An electronic film (E-film) apparatus that reversibly converts a conventional film camera body into an E-film camera is described. The electronic film apparatus includes one or more state sensors that sense the operating state of the camera body. State sensors include an electromagnetic sensor, an acoustic sensor, and/or an optical sensor. The data gathered by the sensors is used to determine the operating state of the camera. Based on the operating state of the camera, the E-film apparatus operates in various power modes, including sleep modes, low power modes, and full power modes. The electromagnetic sensor includes a loop or coil that converts electromagnetic fields into an electrical signal. The acoustic sensor senses vibrations in the camera due to operation of the mechanical aspects of the camera body. The acoustic sensor converts vibrations in the camera body into an electrical signal.

Abstract: A device and method for detecting the presence of nearby aircraft which have a strobe-type, anticollision signalling device with respect to a monitoring aircraft. Incoming radiation is detected, including (i) background radiation (ii) pulse-like radiation occurring in random manner, and (iii) pulse-like radiation characterized by uniform periodic pulse rate. Background radiation is filtered, leaving a signal representing pulse-like radiation occurring either in random manner and/or periodic regularity. Those signals having periodic regularity are identified and recorded as pulse trains which provide the basis for generating an alarm indicating detection of a strobe anticollision device. Additional devices and procedures are applied with respect to the invention to define its accuracy and economy as part of a passive optical traffic alert system for small aircraft.

Abstract: Integrated circuit dies are mounted to the interconnection leads on frames of tape automatic bonding (TAB) film. Thereafter, each frame of the TAB film with the attached integrated circuit die is affixed to an electrically insulating, thermally conductive plate to form a sandwich structure. A number of sandwich structures are bonded together to form a stack of sandwiches. The interconnection leads of each sandwich in the stack are selectively electrically connected to the interconnection leads of other sandwiches in the stack to form a system of electrically interconnected integrated circuits. The system is compact and has short interconnection paths between integrated circuits so that the propagation delays of signals between integrated circuits are minimized.

Abstract: Integrated circuit dies are mounted to the interconnection leads on frames of tape automatic bonding (TAB) film. Thereafter, each frame of the TAB film with the attached integrated circuit die is affixed to an electrically insulating, thermally conductive plate to form a sandwich structure. A number of sandwich structures are bonded together to form a stack of the sandwiches. The interconnection leads of each sandwich in the stack are selectively electrically connected to the interconnection leads of other sandwiches in the stack to form a system of electrically interconnected integrated circuits. The system is compact and has short interconnection paths between integrated circuits so that the propagation delays of signals between integrated circuits are minimized.

Abstract: A multiplexer circuit is disclosed, for use with such signal sources as focal plane detector arrays, which contains a large number of parallel branches, each of which includes a transconductance MOSFET amplifier and a MOSFET switch of opposite channel polarity from the amplifier. The amplifier in each branch receives high impedance voltage signals originating from its individual detector and converts them with high power gain into current signals which feed into the common output line whenever the switch in the same branch is turned on. The multiplexer branches, together with the multiplexer control logic, and other electronic devices, are all included on a signal IC chip which provides CMOS logic.

Abstract: A circuit for controlling the power supplied to a lamp includes a sensor, located at the lamp, which measures the portion of the lamp's output which is reflected from an illuminated area. This sensor is connected to a sensing circuit which measures the reflectance of the illuminated area. Using this reflectance measurement, the total illumination incident on a work space, both from the light source and from other illumination sources, is determined and this total incident illumination is adjusted by adjusting the power supplied to the light source to provide a controlled illumination. The ability to measure reflectance of the illuminated area using a sensor at the light source itself permits the manufacture of a light source which will self-adjust to illuminate a work area at a desired incident illumination level, without adjustment of the light after installation, and without a requirement that the light source be adjusted if the reflectance of the work area changes.

Abstract: An illumination control device for regulating the illumination in a controlled lighting area responds to natural illumination to control artificial lighting. The illumination control device turns the artificial light on and off at independently variable natural illumination levels to provide a hysteresis between the turn-on and turn-off points of the artificial lights. In addition, a variable time delay is included in the illumination control device to delay the turn-off of the lights for a variable period of time after the natural light level has risen above the level required for artificial light turn-off. Furthermore, the illumination control device includes a circuit for turning on all of the lights, regardless of the natural illumination level, when the circuit is initially energized so that the lights can be checked by maintenance personnel.

Abstract: A multiplexer circuit is disclosed, for use with such signal sources as focal plane detector arrays, which contains a large number of parallel branches, each of which includes a transconductance MOSFET amplifier and a MOSFET switch of opposite channel polarity from the amplifier. The amplifier in each branch receives high impedance voltage signals orginating from its individual detector and converts them with high power gain into current signals which feed into the common output line whenever the switch in the same branch is turned on. The multiplexer branches, together with the multiplexer control logic, and other electronic devices, are all included on a signal IC chip which provides CMOS logic.