Abstract: An apparatus for cache coherency between a device and a processor includes a buffer module that buffers data in a non-cache coherent space of an electronic device communicatively coupled to a processor. The apparatus includes an update module that updates at least one identifier with respect to the buffered data. The at least one identifier is stored in a cache coherent space of the electronic device. The apparatus includes a coherence notification module that notifies the processor of a cache incoherence. The cache incoherence indicates that the cache coherent space of the electronic device that includes the updated at least one identifier differs from a cache coherent space of the processor that includes a copy of the at least one identifier prior to the update.

Abstract: Configuring NVMe devices for redundancy and scaling includes: identifying, by a first SSD (‘Solid State Drive’) driver executing on a first CPU (‘Central Processing Unit’), address space of a first SSD coupled to the first CPU by a first PCI (‘Peripheral Component Interconnect’) switch, the first PCI switch including one or more non-transparent bridges (‘NTBs’); partitioning, by the first SSD driver, the address space of the first SSD amongst the NTBs of the first PCI switch and the first CPU, where each NTB is configured to translate CPU memory addresses received from a CPU into a drive address in the address space partitioned to the NTB; and partitioning, by the first SSD driver, a plurality of namespaces of the first SSD amongst the first CPU and the NTBs.

Abstract: An apparatus for cache coherency between a device and a processor includes a buffer module that buffers data in a non-cache coherent space of an electronic device communicatively coupled to a processor. The apparatus includes an update module that updates at least one identifier with respect to the buffered data. The at least one identifier is stored in a cache coherent space of the electronic device. The apparatus includes a coherence notification module that notifies the processor of a cache incoherence. The cache incoherence indicates that the cache coherent space of the electronic device that includes the updated at least one identifier differs from a cache coherent space of the processor that includes a copy of the at least one identifier prior to the update.

Abstract: Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.

Abstract: Configuring NVMe devices for redundancy and scaling includes: identifying, by a first SSD (‘Solid State Drive’) driver executing on a first CPU (‘Central Processing Unit’), address space of a first SSD coupled to the first CPU by a first PCI (‘Peripheral Component Interconnect’) switch, the first PCI switch including one or more non-transparent bridges (‘NTBs’); partitioning, by the first SSD driver, the address space of the first SSD amongst the NTBs of the first PCI switch and the first CPU, where each NTB is configured to translate CPU memory addresses received from a CPU into a drive address in the address space partitioned to the NTB; and partitioning, by the first SSD driver, a plurality of namespaces of the first SSD amongst the first CPU and the NTBs.

Abstract: A method includes running a scale-up hypervisor on a server complex including at least one server and running a single operating system and at least one application on top of the scale-up hypervisor. The method further includes identifying a firmware update available for a first hardware component within the server complex. The scale-up hypervisor removes all workload from the first hardware component, and the identified firmware update is applied to the first hardware component while the first hardware component is idle and the hypervisor continues running the single operating system and the at least one application. Preferably, the method may be used to sequentially apply firmware updates to various hardware components across the plurality of servers without ever shutting down the entire plurality of servers.

Abstract: Hardware component repair in a computing system while workload continues to execute on the computing system includes receiving an indication that an operational parameter of a first hardware resource of said computing system does not meet operational acceptability criteria; migrating workload of the computing system from said first hardware resource to a second hardware resource within the computing system; and halting operation of said first hardware resource for repair.

Abstract: Hardware component repair in a computing system while workload continues to execute on the computing system includes receiving an indication that an operational parameter of a first hardware resource of said computing system does not meet operational acceptability criteria; migrating workload of the computing system from said first hardware resource to a second hardware resource within the computing system; and halting operation of said first hardware resource for repair.

Abstract: A method includes running a scale-up hypervisor on a server complex including at least one server and running a single operating system and at least one application on top of the scale-up hypervisor. The method further includes identifying a firmware update available for a first hardware component within the server complex. The scale-up hypervisor removes all workload from the first hardware component, and the identified firmware update is applied to the first hardware component while the first hardware component is idle and the hypervisor continues running the single operating system and the at least one application. Preferably, the method may be used to sequentially apply firmware updates to various hardware components across the plurality of servers without ever shutting down the entire plurality of servers.

Abstract: Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number of errors associated with the memory page exceeds the predetermined threshold, attempting, by the page management module, to retire the memory page; determining, by the page management module, whether the memory page has been successfully retired; and responsive to determining that the memory page has not been successfully retired, generating, by the page management module, a predictive failure alert.

Abstract: A memory management controller operatively coupled to a plurality of memory modules, the memory management controller including processing logic configured to: identify a plurality of memory tiers in the plurality of memory modules, each memory tier characterized by different operational characteristics; allocate a spare block of memory in each memory tier; identify a data characteristic for each of the one or more blocks of data in a plurality of memory tiers; migrate, in dependence upon the operational characteristics of each memory tier and the data characteristic for each of the one or more data blocks in the plurality of memory tiers, data in a first memory tier to the spare block of memory in a second memory tier; and migrate data in the second memory tier to the spare block of memory in the first memory tier.

Abstract: A memory management controller operatively coupled to a plurality of memory modules, the memory management controller including processing logic configured to: identify a plurality of memory tiers in the plurality of memory modules, each memory tier characterized by different operational characteristics; allocate a spare block of memory in each memory tier; identify a data characteristic for each of the one or more blocks of data in a plurality of memory tiers; migrate, in dependence upon the operational characteristics of each memory tier and the data characteristic for each of the one or more data blocks in the plurality of memory tiers, data in a first memory tier to the spare block of memory in a second memory tier; and migrate data in the second memory tier to the spare block of memory in the first memory tier.

Abstract: Memory bus attached Input/Output (‘I/O’) subsystem management in a computing system, the computing system including an I/O subsystem communicatively coupled to a memory bus, including: detecting, by an I/O subsystem device driver, a hibernation request; setting, by the I/O subsystem device driver, a predetermined memory address to a value indicating that the I/O subsystem is not to service system requests; detecting, by the I/O subsystem device driver, that the I/O subsystem device driver has been restarted; and setting, by the I/O subsystem device driver, the predetermined memory address to a value indicating that the I/O subsystem can resume servicing system requests.

Abstract: Memory bus attached Input/Output (‘I/O’) subsystem management in a computing system, the computing system including an I/O subsystem communicatively coupled to a memory bus, including: detecting, by an I/O subsystem device driver, a hibernation request; setting, by the I/O subsystem device driver, a predetermined memory address to a value indicating that the I/O subsystem is not to service system requests; detecting, by the I/O subsystem device driver, that the I/O subsystem device driver has been restarted; and setting, by the I/O subsystem device driver, the predetermined memory address to a value indicating that the I/O subsystem can resume servicing system requests.

Abstract: Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.

Abstract: Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number of errors associated with the memory page exceeds the predetermined threshold, attempting, by the page management module, to retire the memory page; determining, by the page management module, whether the memory page has been successfully retired; and responsive to determining that the memory page has not been successfully retired, generating, by the page management module, a predictive failure alert.

Abstract: Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number of errors associated with the memory page exceeds the predetermined threshold, attempting, by the page management module, to retire the memory page; determining, by the page management module, whether the memory page has been successfully retired; and responsive to determining that the memory page has not been successfully retired, generating, by the page management module, a predictive failure alert.

Abstract: A memory management controller operatively coupled to a plurality of memory modules, the memory management controller including processing logic configured to: identify a plurality of memory tiers in the plurality of memory modules, each memory tier characterized by different operational characteristics; allocate a spare block of memory in each memory tier; identify a data characteristic for each of the one or more blocks of data in a plurality of memory tiers; migrate, in dependence upon the operational characteristics of each memory tier and the data characteristic for each of the one or more data blocks in the plurality of memory tiers, data in a first memory tier to the spare block of memory in a second memory tier; and migrate data in the second memory tier to the spare block of memory in the first memory tier.

Abstract: A memory management controller operatively coupled to a plurality of memory modules, the memory management controller including processing logic configured to: identify a plurality of memory tiers in the plurality of memory modules, each memory tier characterized by different operational characteristics; allocate a spare block of memory in each memory tier; identify a data characteristic for each of the one or more blocks of data in a plurality of memory tiers; migrate, in dependence upon the operational characteristics of each memory tier and the data characteristic for each of the one or more data blocks in the plurality of memory tiers, data in a first memory tier to the spare block of memory in a second memory tier; and migrate data in the second memory tier to the spare block of memory in the first memory tier.

Abstract: Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.