Patents by Inventor Randon K. Richards

Randon K. Richards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210367057
    Abstract: Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.
    Type: Application
    Filed: August 2, 2021
    Publication date: November 25, 2021
    Inventors: Chan H. Yoo, George E. Pax, Yogesh Sharma, Gregory A. King, Thomas H. Kinsley, Randon K. Richards
  • Patent number: 11177222
    Abstract: Semiconductor devices with antennas and electromagnetic interference (EMI) shielding, and associated systems and methods, are described herein. In one embodiment, a semiconductor device includes a semiconductor die coupled to a package substrate. An antenna structure is disposed over and/or adjacent the semiconductor die. An electromagnetic interference (EMI) shield is disposed between the semiconductor die and the antenna structure to shield at least the semiconductor die from electromagnetic radiation generated by the antenna structure and/or to shield the antenna structure from interference generated by the semiconductor die. A first dielectric material and/or a thermal interface material can be positioned between the semiconductor die and the EMI shield, and a second dielectric material can be positioned between the EMI shield and the antenna structure.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: November 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Dong Soon Lim, Randon K. Richards, Aparna U. Limaye
  • Patent number: 11081565
    Abstract: Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, George E. Pax, Yogesh Sharma, Gregory A. King, Thomas H. Kinsley, Randon K. Richards
  • Publication number: 20210193203
    Abstract: Methods, systems, and apparatuses for managing clock signals at a memory device are described. A memory device or other component of a memory module or electronic system may offset a received clock signal. For example, the memory device may receive a clock signal that has a nominal speed or frequency of operation for a system, and the memory device may adjust or offset the clock signal based on other operating factors, such as the speed or frequency of other signals, physical constraints, indications received from a host device, or the like. A clock offset value may be based on propagation of, for example, command/address signaling. In some examples, a memory module may include a registering clock driver (RCD), hub, or local controller that may manage or coordinate clock offsets among or between various memory devices on the module. Clock offset values may be programmed to a mode register or registers.
    Type: Application
    Filed: March 5, 2021
    Publication date: June 24, 2021
    Inventors: Randon K. Richards, Dirgha Khatri
  • Patent number: 10989748
    Abstract: The present disclosure includes apparatuses and methods related to test devices, for example testing devices by measuring signals emitted by a device. One example apparatus can include a first portion including a number of sidewalls positioned to at least partially surround a device under test; and a second portion electrically coupled to the first portion, wherein the second portion is configured to move in the x-direction, the y-direction, and z-direction.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: April 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Paul E. Gregory, Randon K. Richards
  • Publication number: 20210118849
    Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more stacks of microelectronic devices are located on the substrate, and microelectronic devices of the stacks are connected to vertical conductive paths external to the stacks and extending to the substrate and to lateral conductive paths extending between the stacks. Methods of fabrication are also disclosed.
    Type: Application
    Filed: July 27, 2020
    Publication date: April 22, 2021
    Inventors: Aparna U. Limaye, Dong Soon Lim, Randon K. Richards, Owen R. Fay
  • Publication number: 20210118852
    Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.
    Type: Application
    Filed: July 27, 2020
    Publication date: April 22, 2021
    Inventors: Owen R. Fay, Randon K. Richards, Aparna U. Limaye, Dong Soon Lim, Chan H. Yoo, Bret K. Street, Eiichi Nakano, Shijian Luo
  • Publication number: 20210118851
    Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, at least one surface mount component operably coupled to conductive traces of at least one dielectric material, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate.
    Type: Application
    Filed: July 27, 2020
    Publication date: April 22, 2021
    Inventors: Randon K. Richards, Owen R. Fay, Aparna U. Limaye, Dong Soon Lim
  • Publication number: 20210118850
    Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.
    Type: Application
    Filed: July 27, 2020
    Publication date: April 22, 2021
    Inventors: Randon K. Richards, Aparna U. Limaye, Owen R. Fay, Dong Soon Lim
  • Patent number: 10943628
    Abstract: Methods, systems, and apparatuses for managing clock signals at a memory device are described. A memory device or other component of a memory module or electronic system may offset a received clock signal. For example, the memory device may receive a clock signal that has a nominal speed or frequency of operation for a system, and the memory device may adjust or offset the clock signal based on other operating factors, such as the speed or frequency of other signals, physical constraints, indications received from a host device, or the like. A clock offset value may be based on propagation of, for example, command/address signaling. In some examples, a memory module may include a registering clock driver (RCD), hub, or local controller that may manage or coordinate clock offsets among or between various memory devices on the module. Clock offset values may be programmed to a mode register or registers.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Randon K. Richards, Dirgha Khatri
  • Publication number: 20210035617
    Abstract: Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.
    Type: Application
    Filed: August 2, 2019
    Publication date: February 4, 2021
    Inventors: Eric J. Stave, George E. Pax, Yogesh Sharma, Gregory A. King, Chan H. Yoo, Randon K. Richards, Timothy M. Hollis
  • Publication number: 20210036125
    Abstract: Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.
    Type: Application
    Filed: August 2, 2019
    Publication date: February 4, 2021
    Inventors: Chan H. Yoo, George E. Pax, Yogesh Sharma, Gregory A. King, Thomas H. Kinsley, Randon K. Richards
  • Publication number: 20210035917
    Abstract: Semiconductor devices with antennas and electromagnetic interference (EMI) shielding, and associated systems and methods, are described herein. In one embodiment, a semiconductor device includes a semiconductor die coupled to a package substrate. An antenna structure is disposed over and/or adjacent the semiconductor die. An electromagnetic interference (EMI) shield is disposed between the semiconductor die and the antenna structure to shield at least the semiconductor die from electromagnetic radiation generated by the antenna structure and/or to shield the antenna structure from interference generated by the semiconductor die. A first dielectric material and/or a thermal interface material can be positioned between the semiconductor die and the EMI shield, and a second dielectric material can be positioned between the EMI shield and the antenna structure.
    Type: Application
    Filed: July 29, 2019
    Publication date: February 4, 2021
    Inventors: Owen R. Fay, Dong Soon Lim, Randon K. Richards, Aparna U. Limaye
  • Publication number: 20210037679
    Abstract: Systems, apparatuses, and methods for thermal dissipation on or from an electronic device are described. For example, a memory module may have a printed circuit board (PCB) having an edge connector, a plurality of memory devices disposed on a surface of the PCB, and a tubular heat spreader disposed along an edge of the PCB opposite the edge connector. The tubular heat spreader may comprise a tubular portion open at both ends thereof to permit the through flow of a cooling gas; and two planar elements extending in parallel away from the tubular portion and configured to provide a friction fit with the memory module. Each of the planar elements may be configured to convey thermal energy from the memory module to the tubular portion.
    Type: Application
    Filed: August 2, 2019
    Publication date: February 4, 2021
    Inventors: Thomas H. Kinsley, George E. Pax, Yogesh Sharma, Gregory A. King, Chan H. Yoo, Randon K. Richards
  • Publication number: 20210027816
    Abstract: Methods, systems, and apparatuses for managing clock signals at a memory device are described. A memory device or other component of a memory module or electronic system may offset a received clock signal. For example, the memory device may receive a clock signal that has a nominal speed or frequency of operation for a system, and the memory device may adjust or offset the clock signal based on other operating factors, such as the speed or frequency of other signals, physical constraints, indications received from a host device, or the like. A clock offset value may be based on propagation of, for example, command/address signaling. In some examples, a memory module may include a registering clock driver (RCD), hub, or local controller that may manage or coordinate clock offsets among or between various memory devices on the module. Clock offset values may be programmed to a mode register or registers.
    Type: Application
    Filed: July 22, 2019
    Publication date: January 28, 2021
    Inventors: Randon K. Richards, Dirgha Khatri
  • Publication number: 20200348349
    Abstract: The present disclosure includes apparatuses and methods related to test devices, for example testing devices by measuring signals emitted by a device. One example apparatus can include a first portion including a number of sidewalls positioned to at least partially surround a device under test; and a second portion electrically coupled to the first portion, wherein the second portion is configured to move in the x-direction, the y-direction, and z-direction.
    Type: Application
    Filed: July 17, 2020
    Publication date: November 5, 2020
    Inventors: Paul E. Gregory, Randon K. Richards
  • Patent number: 10718805
    Abstract: The present disclosure includes apparatuses and methods related to test devices, for example testing devices by measuring signals emitted by a device. One example apparatus can include a first portion including a number of sidewalls positioned to at least partially surround a device under test; and a second portion electrically coupled to the first portion, wherein the second portion is configured to move in the x-direction, the y-direction, and z-direction.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: July 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Paul E. Gregory, Randon K. Richards
  • Publication number: 20200201807
    Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 25, 2020
    Inventors: Thomas H. Kinsley, George E. Pax, Timothy M. Hollis, Yogesh Sharma, Randon K. Richards, Chan H. Yoo, Gregory A. King, Eric J. Stave
  • Publication number: 20170356946
    Abstract: The present disclosure includes apparatuses and methods related to test devices, for example testing devices by measuring signals emitted by a device. One example apparatus can include a first portion including a number of sidewalls positioned to at least partially surround a device under test; and a second portion electrically coupled to the first portion, wherein the second portion is configured to move in the x-direction, the y-direction, and z-direction.
    Type: Application
    Filed: May 26, 2017
    Publication date: December 14, 2017
    Inventors: Paul E. Gregory, Randon K. Richards