Abstract: A semiconductor device aluminum-containing metallization system that is particularly useful for integrated circuits (ICs) having P-type contact regions and also having a likelihood of extended exposure to elevated temperatures. Use of an aluminum/silicon diffusion barrier formed of an amorphous tungsten/silicon on such ICs is made commercially practical. A titanium or transition metal silicide layer is disposed beneath the amorphous tungsten/silicon layer, to consistently provide durable low resistance electrical contacts to P-type regions of the IC.

Abstract: A process for fabricating a high voltage CMOS transistor having a non-self aligned implanted channel which permits the operation of the device at high voltages. The non-self aligned implanted channel does not require alignment with the gate electrode of the CMOS device, but is accurately implanted early in the fabrication of the device through reliance on direct wafer stepper technology. As a result, the non-self aligned implanted channel does not require a high temperature drive, such that fabrication of the transistor is compatible with VLSI and ULSI processes, and the transistor can be up-integrated onto logic integrated circuits. Accuracy of the placement of the non-self aligned implanted channel provides for a shorter channel length, which enables the device to be highly area efficient while also increasing the current capability of the device.

Abstract: The present invention relates to an integrated circuit which includes complementary MOS transistors (e.g., a CMOS circuit), an EEPROM, and to a method of making the integrated circuit. The EEPROM is incorporated in the circuit in such a manner that it does not adversely affect the high performance, low voltage operation of the CMOS circuit. Also, the EEPROM is designed so that it is programmable at a low voltage which is compatible with the low voltages typically used with the CMOS circuit. The EEPROM includes a floating gate and a control gate which have a large area of overlap so as to provide a high capacitance therebetween. This provides a high ratio (e.g., about two or greater) of the floating gate to control gate capacitance divided by the floating gate to substrate capacitance to provide the EEPROM with the low voltage operation. To make the integrated circuit, standard CMOS process steps using design rules of about two microns or less are used to make the MOS transistors.

Abstract: The present invention relates to an integrated circuit which includes complementary MOS transistors (e.g., a CMOS circuit), an EEPROM, and to a method of making the integrated circuit. The EEPROM is incorporated in the circuit in such a manner that it does not adversely affect the high performance, low voltage operation of the CMOS circuit. Also, the EEPROM is designed so that it is programmable at a low voltage which is compatible with the low voltages typically used with the CMOS circuit. The EEPROM includes a floating gate and a control gate which have a large area of overlap so as to provide a high capacitance therebetween. This provides a high ratio (e.g., about two or greater) of the floating gate to control gate capacitance divided by the floating gate to substrate capacitance to provide the EEPROM with the low voltage operation. To make the integrated circuit, standard CMOS process steps using design rules of about two microns or less are used to make the MOS transistors.

Abstract: An integrated circuit is made that includes an insulated gate transistor and a buried contact. The buried contact is used to divide an active device area in two discrete parts, that are doped during source-drain doping in other active device mesas of the integrated circuit. Discrete contacts to these regions, along with the buried contact, provide an additional type of electrical component in the integrated circuit, such as a bipolar lateral transistor.

Abstract: An enhancement implant used in late programming of a ROM in an integrated circuit is combined with a depletion implant used much earlier in the fabrication process to also permit late programming of power paths in the integrated circuit. The implants must be matched and the IC heated after the enhancement implant.

Abstract: An integrated circuit is made that includes an insulated gate transistor and a buried contact. The buried contact is used to divide an active device area in two discrete parts, that are doped during source-drain doping in other active device mesas of the integrated circuit. Discrete contacts to these regions, along with the buried contact, provide an additional type of electrical component in the integrated circuit, such as a bipolar lateral transistor.

Abstract: A method of making a strain gauge in a fragile web wherein the improvement resides in making the web after the gauge is substantially completely formed. This reverse sequence is made possible by a unique combination of plasma deposited silicon oxide and plasma deposited silicon nitride on top of the completed device to protect it from attack during silicon substrate etching to form the diaphragm.