Abstract: A circuit for converting received domino logic signals to a static output signal includes a pair of logic gates having inputs and outputs that are cross-coupled and responsive to a domino logic input signal and a clock signal to latch the input signal during an evaluation phase defined by the clock signal. A static output is based on the latched value. One of the logic gates is tri-stateable to establish a value at the static output during a scan mode. A circuit for converting received static logic signals into domino logic signals includes a latch responsive to a clock signal to latch the value of a data signal at a predefined clock transition. A conversion circuit produces a domino logic output signal in response to the clock signal and the latched value of the data signal. A latch component is tri-stateable to establish a value at the output.

Abstract: A circuit for converting received domino logic signals to a static output signal includes a pair of logic gates having inputs and outputs that are cross-coupled and responsive to a domino logic input signal and a clock signal to latch the input signal during an evaluation phase defined by the clock signal. A static output is based on the latched value. One of the logic gates is tri-stateable to establish a value at the static output during a scan mode. A circuit for converting received static logic signals into domino logic signals includes a latch responsive to a clock signal to latch the value of a data signal at a predefined clock transition. A conversion circuit produces a domino logic output signal in response to the clock signal and the latched value of the data signal. A latch component is tri-stateable to establish a value at the output.

Abstract: A circuit is provided for using the input operands of a floating point addition or subtraction operation to detect the leading one or zero bit position in parallel with the arithmetic operation. This allows the alignment to be performed on the available result in the next cycle of the floating point operation and results in a significant performance advantage. The leading I/O detection is decoupled from the adder that is computing the result in parallel, eliminating the need for special circuitry to compute a carry-dependent adjustment signal. The single-bit fraction overflow that can result from leading I/O misprediction is corrected with existing circuitry during a later stage of computation.