Abstract: Multi-function input pins in a programmable logic device are connected to select circuitry which is programmed at device program time. Output signals generated by one or more output logic macrocells are also connected to such select circuitry. The select circuitry generates a signal which is used to drive a row of the array. If an input pin is used for providing a control signal, it is not connected to the array, and the output circuitry can drive that row of the array with an output signal which it generates, or with an input signal obtained from an associated input/output pin.

Abstract: A circuit for generating a reset signal on chip power-up includes two field effect devices connected between a power supply voltage and the input to an inverter. A capacitor is connected between the inverter input and the low supply voltage. Current flows through the field effect devices to charge the transistor only when the supply voltages are greater than the sum of the absolute values of their threshold voltages. The output of the inverter is used as the chip power-up reset signal.

Abstract: A standard logic block, or macrocell, is provided for use on programmable logic devices. The macrocell uses RAM to perform logic functions, and further includes circuitry which allows writing of data to the RAM during use. Each logic block can be configured at programming time to be either a user RAM, allowing the user to write data to such memory during use, or configured as performing logic functions. The contents of macrocells configured as providing logic functions cannot be changed except by reprogramming the device.

Abstract: A Programmable Logic Device includes a programmable array arranged in columns and rows. A sense amplifier is connected to each column of the programmable array and includes a power terminal, a grounding terminal, and a programmable switch connecting between the amplifier common line and the grounding terminal.

Abstract: A programmable logic device includes a programmable logic array and an output logic macrocell. The output logic macrocell includes a user configurable summing function that has a first logic gate connected to receive a first plurality of product terms, a second logic gate connected to receive a second plurality of product terms and a third logic gate connected to receive the combination of the first plurality of product terms and a controls signal, a fourth logic gate connected to receive the combination of the second plurality of Product Terms and the control signal and a logic circuit connected to receive the output signals from the first, second, third and fourth logic gates and to provide a first logical combination when the control signal is at a first logic state and a second logical combination when the controls signal is at a second logic state.