Abstract: A computer system according to the invention includes a posted write cache for writing to a mass storage subsystem. Upon restart, the computer system determines whether the mass storage subsystem has been interveningly written to by another computer system since the computer system last wrote to that mass storage subsystem. If so, the computer system flushes its posted write cache, thus prevent invalid data from being written to the mass storage subsystem.

Abstract: An adaptive read ahead cache is provided with a real cache and a virtual cache. The real cache has a data buffer, an address buffer, and a status buffer. The virtual cache contains only an address buffer and a status buffer. Upon receiving an address associated with the consumer's request, the cache stores the address in the virtual cache address buffer if the address is not found in the real cache address buffer and the virtual cache address buffer. Further, the cache fills the real cache data buffer with data responsive to the address from said memory if the address is found only in the virtual cache address buffer. The invention thus loads data into the cache only when sequential accesses are occurring and minimizes the overhead of unnecessarily filling the real cache when the host is accessing data in a random access mode.

Abstract: A computer system according to the invention includes a posted write cache for writing to a mass storage subsystem. Upon restart, the computer system determines whether the mass storage subsystem has been interveningly written to by another computer system since the computer system last wrote to that mass storage subsystem. If so, the computer system flushes its posted write cache, thus prevent invalid data from being written to the mass storage subsystem.

Abstract: A host computer including a posted write cache for a disk drive system where the posted write cache includes battery backup to protect against potential loss of data in case of a power failure, and also including means for performing a method for determining if live data is present in the posted write cache upon power-up. The posted write cache is further mirrored and parity-checked to assure data validity. Performance increase is achieved since during normal operation data is written to the much faster cache and a completion indication is returned, and the data is flushed to the slower disk drive system at a more opportune time. Batteries provide power to the posted write cache in the event of a power failure. Upon subsequent power-up, a cache signature previously written in the posted write cache indicates that live data still resides in the posted write cache. If the cache signature is not present and the batteries are not fully discharged, a normal power up condition exists.

Abstract: A posting memory used in conjunction with a drive array to increase the performance of fault tolerant disk array write operations. When the posting memory flushes dirty data back to the disk array, the posting memory coalesces or gathers contiguous small write or partial stripe write requests into larger, preferably full stripe writes. This reduces the number of extra read operations necessary to update parity information. In this manner, the actual number of reads and writes to the disk array to perform the transfer of write data to the disk array is greatly reduced. In addition, when the posting memory is full, the posting memory delays small, i.e., partial stripe writes but allows full stripe writes or greater to pass directly to the disk array. This reduces the frequency of partial stripe writes and increases disk array performance.