Abstract: Methods and approaches for fabricating floating gate NAND cells and associated memory devices. A stacked layer structure comprising alternating layers of polysilicon and silicon nitride is fabricated, and an array of memory hole passing vertically through the alternating layers of polysilicon and silicon nitride are formed. Multiple films of materials, such as silicon oxide, silicon nitrides, and polysilicon are sequentially formed over sidewalls of the memory holes during in-memory hole processing. The back-side processing begins with removal of silicon nitride layers (dielectric spacers between wordlines) using an etchant introduced through replacement holes which enables inter-wordline airgaps between FG memory cells in adjacent polysilicon layers. Etching processes selective to silicon oxide and silicon nitride are performed to form the gate, inter-poly dielectric (IPD) layers, and the storage node of the FG memory cells.

Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.

Abstract: Methods and apparatus of engineered dielectric profile for high aspect-ratio (AR) 3D NAND structures. The 3D NAND structures comprise a semiconductor structure having multiple stacked memory tiers comprising 2D arrays of memory cells that are charged using vertical structures formed in the semiconductor structure. The memory tiers comprise wordline layers interposed between isolation layers. The vertical structures, such as memory holes or trenches, have a dielectric (e.g., a tunnel dielectric) formed along sidewalls of holes or trenches having a cross-section profile where a thickness of the dielectric at a bottom wordline layer is thicker than the dielectric thickness for at least a portion of wordline layers above the bottom wordline layer. In one example, formation of the tunnel dielectric employs a sandwich design of engineered profile method in which a selective deposition of dielectric is deposited at the bottom sections of the vertical structures while the rest of the structure is un-altered.

Abstract: Vertical wordline driver structures and methods. The vertical wordline driver comprises a transistor that is used to drive a wordline in a three-dimensional 3D memory structure. A vertical transistor structure is formed in a semiconductor substrate comprising a gate all around (GAA) structure or a double-gate structure including a gate oxide, an amorphous IGZO (Indium Gallium Zinc Oxide) channel, adjacent to the gate oxide, and a liner adjacent to the amorphous IGZO channel. The GAA structure may comprise a conical frustrum shape or a cylindrical shape with straight walls. The double-gate structure may have straight or angled walls. An outer wall of the gate oxide is in contact with a polysilicon gate layer. An upper and lower contact is electrically coupled to the amorphous IGZO channel.

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

Abstract: A vertical channel of a three-dimensional (3D) NAND has a recessed and filled drain/source pocket region for each memory cell to reduce resistance in a region that traditionally has high resistance. The vertical channel conducts current whose resistivity is controlled through a series of memory cells. The vertical channel can have a polysilicon material to conduct current past the memory cell gates and drain/sources region between the memory elements. The recess can extend the polysilicon away from a center of the vertical channel and closer to the control gates. The recess includes a structure to reduce resistance in the drain/source region along the vertical channel between memory cell gates.

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.

Abstract: Storage node configurations are described. A storage node (e.g., a floating gate or a charge trap layer of a three-dimensional (3D) NAND flash device) include a channel-facing surface with a radius of curvature. For example, a channel-facing surface of the storage node may be concave. A control gate-facing surface of the storage node may instead, or additionally, also include a radius of curvature. The radius of curvature of the channel-facing and/or control gate-facing surfaces of the storage node is less than or equal to the radius of the channel layer.

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.

Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.

Abstract: An apparatus is described having a memory. The memory includes a vertical stack of storage cells, where, a first storage node at a lower layer of the vertical stack has a different structural design than a second storage node at a higher layer of the vertical stack.

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.

Abstract: An embodiment of a method of forming a portion of a memory array includes forming a conductor with a concentration of germanium that decreases with an increasing thickness of the conductor, removing a portion of the conductor at a rate governed by the concentration of germanium to form a tapered first opening through the conductor, removing a sacrificial material below the conductor to form a second opening contiguous with the tapered first opening, and forming a semiconductor in the contiguous first and second openings, wherein a portion of the semiconductor pinches off within the first opening adjacent an upper surface of the conductor before the contiguous first and second openings are completely filled with the semiconductor.