Abstract: A parallel calibration system for an electronic circuit tester comprises test and measurement electronics, a test fixture coupled to the test and measurement electronics, the test fixture comprising clock reference circuitry and clock distribution circuitry, a device under test interface, and a plurality of calibration boards coupled to the device under test interface, wherein the plurality of calibration boards and the clock distribution circuitry simultaneously test the signal paths of a plurality of test channels.

Abstract: A trigger signal for a memory tester uses a (breakpoint) trigger qualified according to what part of the test program is being executed. The qualified breakpoint trigger can be delayed before becoming a system trigger signal that can be used to trigger a ‘scope mode and to force an error flag to a selected value so as to compel a particular path with the test program. To provide stable waveforms for the sweeping of the voltage thresholds and sample timing offset the memory tester records the addresses for a target sequence of transmit vectors issued during an initial pass through the test program subsequent to the occurrence of the trigger. These addresses are exchanged for the instructions themselves, which are then altered to remove branching, and stored in a reserved portion of the memory they came from. Once the altered target sequence is stored the desired information is produced by restarting the entire test program and letting it run exactly as before down to the trigger.

Abstract: A memory tester supports testing of multiple DUT's of the same type at a test site. The tester can be instructed to replicate the segments of the test vectors needed to test one DUT on the channels for the other DUT's. This produces patterns of transmit and receive vectors that are n-many DUT's wide. Conditional branching within the test program in response to conditions in the receive vectors (DUT failure) is supported by recognizing several types of error indications and an ability to selectively disable the testing of one or more DUT's while continuing to test the one or more that are not disabled. Also included are ways to remove or limit stimulus to particular DUT's, and ways to make all comparisons for a particular DUT appear to be “good.

Abstract: Systems and methods for calibrating the timing of electronic circuit testers and verifying the timing calibration of electronic circuit testers are described. In some embodiments, a calibration reference signal is transmitted from the test head directly through the load board interface, rather than through external instruments, so that timing errors associated with external wires and cables may be avoided. The timing calibration and timing calibration verification functionality is provided on a single calibration board, thereby reducing the calibration set-up time relative to conventional robot-based calibrators. In addition, a high pin count electronic circuit testers may be calibrated by a calibration board that is configured to calibrate one subset of the test channels at a time.

Abstract: Systems and methods for calibrating the timing of electronic circuit testers and verifying the timing calibration of electronic circuit testers are described. In some embodiments, a calibration reference signal is transmitted from the test head directly through the load board interface, rather than through external instruments, so that timing errors associated with external wires and cables may be avoided. The timing calibration and timing calibration verification functionality is provided on a single calibration board, thereby reducing the calibration set-up time relative to conventional robot-based calibrators. In addition, a high pin count electronic circuit testers may be calibrated by a calibration board that is configured to calibrate one subset of the test channels at a time.

Abstract: A trigger signal for a memory tester having algorithmic test programs detects the occurrence of a trigger specification expressed in terms of existing hardware quantities used to operate the DUT. This forms a raw hardware (breakpoint) trigger that can be further qualified according to what part of the test program is being executed. The qualified breakpoint trigger can be delayed by zero or more DUT cycles before becoming a system trigger signal that can be used to trigger a ‘scope mode and to force an error flag to a selected value so as to compel a particular path with the test program. A user interacts with a process not part of the test program to define a trigger specification from masks and comparison mechanisms that recognize the raw trigger condition at the level of the hardware register values. That process also informs the compiler as to which portions of the test program are to enable the raw trigger specification (done by setting a bit in the instruction word).

Abstract: A precision delay system allowing clock edges to be delayed with new delay values every clock period T. The internal delay elements are reprogrammed every clock cycle with reprogramming transients suppressed by clock independent blanking circuitry. The system allows the use of delay elements with a maximum delay of one-half (T/2) the clock period to continuously span a full clock cycle T delay range with full cycle-by-cycle reprogramming.

Abstract: An improved method of incorporating a high performance graphics device into a base graphics subsystem of a processor includes two pairs of interface chips. One pair of interface chips is used to transfer pixel data between a base graphics system and the high performance graphics device, while the second pair of interface chips is used to transfer commands between the graphics device and the base graphics system. One of the pair of interface chips that is used to transfer pixel data is coupled to a bus within the base graphics subsystem while the second one of the pair is coupled to the graphics device. With such an arrangement, a high speed interface allows for pixel data to be fed directly to the frame buffer of the graphics subsystem, enabling the windows that are rendered by two different graphics systems to share a frame buffer memory.

Abstract: An iconic programming system that provides a sequencer icon to allow a series of operations to be performed, along with the conditions under which the operations are performed. Each operation performed, called a transaction, can be enabled or disabled, or can be enabled by a function within the process. The results of each transaction can be compared to tolerance limits and alternate subsequent transactions processed based upon whether the transaction results fell within the tolerance limits. The output of each transaction can be logged into a buffer to keep the results for later analysis.