Abstract: A method and an apparatus to process read data return has been disclosed. In one embodiment, the method includes packing a cache line of each of a number of read data returns into one or more packets, splitting each of the one or more packets into a plurality of flits, and interleaving the plurality of flits of each of the plurality of read data returns. Other embodiments are described and claimed.

Abstract: Memory device having banks of memory cells organized into two groups of banks that share control circuitry and a data buffer to provide an interface to a memory bus, but which are independently operable enough to support unrelated transactions with each group, and can be used to stagger read operations with shortened burst transfers so as to minimize dead time on a memory bus.

Abstract: Embodiments of the present invention provide an algorithm for scheduling read and write transactions to memory out of order to improve command and data bus utilization and gain performance over a range of workloads. In particular, memory transactions are sorted into queues so that they do not have page conflict with each other and are scheduled from these queues out of order in accordance with read and write scheduling algorithms to optimize latency.

Abstract: Apparatus and method for using a precharge command in which a plurality of address lines are individually used to specify which banks of memory cells within a memory device have an open row that is to be closed.

Abstract: Apparatus and method to implicitly transmit a command to close a row of memory cells within a memory device as part of the transmission of an activate command to open another row of memory cells within the memory device.