Patents by Inventor Randy William Mann
Randy William Mann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7745863Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.Type: GrantFiled: June 26, 2008Date of Patent: June 29, 2010Assignee: International Business Machines CorporationInventors: James W. Adkisson, Charles Thomas Black, Alfred Grill, Randy William Mann, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Publication number: 20090080276Abstract: A circuit is disclosed which generates such a bias voltage that when this bias voltage is received by a large plurality of devices of a semiconductor chip, power consumption is reduced in the stand-by mode at any particular operating temperature. The disclosed circuit contains at least one monitor FET, which is kept in its off-state, and which has common properties with the large plurality of FET devices. The temperature dependent leakage current of the monitor FET is sensed, and used to generate the bias voltage in proportion to the leakage current. This bias voltage is received by the large plurality FET devices on their gate electrodes, or on their body terminals.Type: ApplicationFiled: September 23, 2007Publication date: March 26, 2009Inventors: Jin Cai, Randy William Mann, Harold Pilo
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Publication number: 20080258194Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.Type: ApplicationFiled: June 26, 2008Publication date: October 23, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James William Adkisson, Charles Thomas Black, Alfred Grill, Randy William Mann, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Patent number: 7402857Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.Type: GrantFiled: March 16, 2007Date of Patent: July 22, 2008Assignee: International Business Machines CorporationInventors: James W. Adkisson, Charles Thomas Black, Alfred Grill, Randy William Mann, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Publication number: 20080124880Abstract: Some non-limiting example embodiments comprise a disposable spacer formation and removal process and a stress capping layer process. We provide a gate structure over a substrate. We form disposable spacers abutting the at least one gate sidewall. We form S/D regions adjacent the disposable spacers. We remove the disposable spacers. We can form silicide regions over the S/D and gate. In an aspect, we can deposit a stress inducing layer over the gate and surface portions of the substrate adjacent to the gate, wherein the stress inducing liner provides a stress to a portion of the substrate underlying the gate electrode.Type: ApplicationFiled: September 23, 2006Publication date: May 29, 2008Applicants: Chartered Semiconductor Manufacturing Ltd., International Business Machines CorporationInventors: Wenhe Lin, Randy William Mann, Padraic C. Shafer, Christopher Vincent Baiocco, Zhijoing Luo, Haining S. Yang, Xiangdong Chen
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Patent number: 7217969Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.Type: GrantFiled: March 7, 2003Date of Patent: May 15, 2007Assignee: International Business Machines CorporationInventors: James William Adkisson, Charles Thomas Black, Alfred Grill, Randy William Mann, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Patent number: 7186573Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.Type: GrantFiled: October 31, 2005Date of Patent: March 6, 2007Assignee: International Business Machines CorporationInventors: James William Adkisson, Charles Thomas Black, Alfred Grill, Randy William Mann, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Patent number: 6774017Abstract: A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the trench isolation structure may vary with depth. The trench isolation structure may touch or not touch the buried oxide layer. Two trench isolation structures may penetrate the substrate to the same depth or to different depths. The trench isolation structures provide insulative separation between regions within the substrate and the separated regions may contain semiconductor devices. The semiconductor structure facilitates the providing of digital and analog devices on a common wafer. A dual-depth buried oxide layer facilitates an asymmetric semiconductor structure.Type: GrantFiled: July 3, 2002Date of Patent: August 10, 2004Assignee: International Business Machines CorporationInventors: Jeffrey Scott Brown, Andres Bryant, Robert J. Gauthier, Jr., Randy William Mann, Steven Howard Voldman
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Patent number: 6614124Abstract: An SRAM memory cell device comprises wordline and bitline inputs for enabling read/write access to memory cell contents, and, a diffusion region for maintaining a voltage to preserve memory cell content when the cell is not being accessed. The device further comprises a transistor device having a gate input for receiving a wordline voltage to turn off the transistor device when not performing memory cell read/write access; and, a gate oxide layer formed under the transistor device gate exhibiting resistance property for leaking current therethrough when the wordline voltage is applied to the gate input and the transistor device is off. The diffusion region receives voltage derived from the wordline voltage applied to said gate input to enable retention of said memory cell content in the absence of applied bitline voltage to thereby reduce power consumption.Type: GrantFiled: November 28, 2000Date of Patent: September 2, 2003Assignee: International Business Machines CorporationInventors: Jeffrey Scott Brown, Chung Hon Lam, Randy William Mann
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Publication number: 20030155598Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.Type: ApplicationFiled: March 7, 2003Publication date: August 21, 2003Applicant: International Business Machines CorporationInventors: James William Adkisson, Charles Thomas Black, Alfred Grill, Randy William Mann, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Patent number: 6555859Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.Type: GrantFiled: August 8, 2001Date of Patent: April 29, 2003Assignee: International Business Machines CorporationInventors: James William Adkisson, Charles Thomas Black, Alfred Grill, Randy William Mann, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Patent number: 6498096Abstract: A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.Type: GrantFiled: March 8, 2001Date of Patent: December 24, 2002Assignee: International Business Machines CorporationInventors: James Allan Bruce, Jonathan Daniel Chapple-Sokol, Charles W. Koburger, III, Michael James Lercel, Randy William Mann, James Spiros Nakos, John Joseph Pekarik, Kirk David Peterson, Jed Hickory Rankin
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Publication number: 20020175413Abstract: A method of forming a liner (and resultant structure) in a contact includes depositing a first layer of refractory metal, annealing the first layer, and sputter depositing a second layer of refractory metal or a compound or an alloy thereof, over the first layer.Type: ApplicationFiled: March 29, 2001Publication date: November 28, 2002Applicant: International Business Machines CorporationInventors: Louis D. Lanzerotti, Randy William Mann, Glen Lester Miles, William Joseph Murphy, Daniel Scott Vanslette
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Publication number: 20020167050Abstract: A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the trench isolation structure may vary with depth. The trench isolation structure may touch or not touch the buried oxide layer. Two trench isolation structures may penetrate the substrate to the same depth or to different depths. The trench isolation structures provide insulative separation between regions within the substrate and the separated regions may contain semiconductor devices. The semiconductor structure facilitates the providing of digital and analog devices on a common wafer. A dual-depth buried oxide layer facilitates an asymmetric semiconductor structure.Type: ApplicationFiled: July 3, 2002Publication date: November 14, 2002Inventors: Jeffrey Scott Brown, Andres Bryant, Robert J. Gauthier, Randy William Mann, Steven Howard Voldman
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Patent number: 6476445Abstract: A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the trench isolation structure may vary with depth. The trench isolation structure may touch or not touch the buried oxide layer. Two trench isolation structures may penetrate the substrate to the same depth or to different depths. The trench isolation structures provide insulative separation between regions within the substrate and the separated regions may contain semiconductor devices. The semiconductor structure facilitates the providing of digital and analog devices on a common wafer. A dual-depth buried oxide layer facilitates an asymmetric semiconductor structure.Type: GrantFiled: April 30, 1999Date of Patent: November 5, 2002Assignee: International Business Machines CorporationInventors: Jeffrey Scott Brown, Andres Bryant, Robert J. Gauthier, Jr., Randy William Mann, Steven Howard Voldman
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Publication number: 20020028549Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.Type: ApplicationFiled: August 8, 2001Publication date: March 7, 2002Applicant: International Business Machines CorporationInventors: James William Adkisson, Charles Thomas Black, Alfred Grill, Randy William Mann, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Patent number: 6333202Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.Type: GrantFiled: August 26, 1999Date of Patent: December 25, 2001Assignee: International Business Machines CorporationInventors: James William Adkisson, Charles Thomas Black, Alfred Grill, Randy William Mann, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Patent number: 6294419Abstract: A method and structure for improving the latch-up characteristic of semiconductor devices is provided. A dual depth STI is used to isolate the wells from each other. The trench has a first substantially horizontal surface at a first depth and a second substantially horizontal surface at a second depth which is deeper than the first depth. The n- and p-wells are formed on either side of the trench. A highly doped region is formed in the substrate underneath the second substantially horizontal surface of the trench. The highly doped region abuts both the first and the second wells and extends the isolation of the trench.Type: GrantFiled: November 6, 2000Date of Patent: September 25, 2001Assignee: International Business Machines CorporationInventors: Jeffrey Scott Brown, Robert J. Gauthier, Jr., Randy William Mann, Steven Howard Voldman
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Publication number: 20010019886Abstract: A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.Type: ApplicationFiled: March 8, 2001Publication date: September 6, 2001Applicant: International Business Machines CorporationInventors: James Allan Bruce, Jonathan Daniel Chapple-Sokol, Charles W. Koburger, Michael James Lercel, Randy William Mann, James S. Nakos, John Joseph Pekarik, Kirk David Peterson, Jed Hickory Rankin
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Patent number: 6215190Abstract: A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.Type: GrantFiled: May 12, 1998Date of Patent: April 10, 2001Assignee: International Business Machines CorporationInventors: James Allen Bruce, Jonathan Daniel Chapple-Sokol, Charles W. Koburger, III, Michael James Lercel, Randy William Mann, James Spiros Nakos, John Joseph Prxarik, Kirk David Peterson, Jed Hickory Rankin