Patents by Inventor Randy Yim

Randy Yim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of using a test reticle to optimize alignment of integrated circuit process layers
    Patent number: 5898478
    Abstract: A test reticle and alignment mark optimization method is provided for determining the optimal alignment mark size for the efficient and accurate alignment of process layers during integrated circuit manufacture. The test reticle includes a number of orthogonally arranged alignment marks of various types and sizes and one or more registration structures. The method involves the steps of determining an initial expected range of alignment mark sizes on the test reticle which are suitable for a particular application; applying the test reticle patter to test wafers; further processing the test wafers; measuring the alignment signals produced by scanning the alignment marks in the initial expected range; quantifying the alignment signal quality; and fitting the quantified alignment signal quality to a statistical model to determine a range of optimal alignment signal dimensions.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: April 27, 1999
    Assignee: LSI Logic Corporation
    Inventors: Randy Yim, Christopher Neville
  • Integrated circuit test reticle and alignment mark optimization method
    Patent number: 5627624
    Abstract: A test reticle and alignment mark optimization method is provided for determining the optimal alignment mark size for the efficient and accurate alignment of process layers during integrated circuit manufacture. The test reticle includes a number of orthogonally arranged alignment marks of various types and sizes and one or more registration structures. The method involves the steps of determining an initial expected range of alignment mark sizes on the test reticle which are suitable for a particular application; applying the test reticle patter to test wafers; further processing the test wafers; measuring the alignment signals produced by scanning the alignment marks in the initial expected range; quantifying the alignment signal quality; and fitting the quantified alignment signal quality to a statistical model to determine a range of optimal alignment signal dimensions.
    Type: Grant
    Filed: October 31, 1994
    Date of Patent: May 6, 1997
    Assignee: LSI Logic Corporation
    Inventors: Randy Yim, Christopher Neville
  • Integrated circuit test reticle and alignment mark optimization method
    Patent number: 5329334
    Abstract: A test reticle and alignment mark optimization method is provided for determining the optimal alignment mark size for the efficient and accurate alignment of process layers during integrated circuit manufacture. The test reticle includes a number of orthogonally arranged alignment marks of various types and sizes and one or more registration structures. The method involves the steps of determining an initial expected range of alignment mark sizes on the test reticle which are suitable for a particular application; applying the test reticle pattern to test wafers; further processing the test wafers; measuring the alignment signals produced by scanning the alignment marks in the initial expected range; quantifying the alignment signal quality; and fitting the quantified alignment signal quality to a statistical model to determine a range of optimal alignment signal dimensions.
    Type: Grant
    Filed: March 2, 1993
    Date of Patent: July 12, 1994
    Assignee: LSI Logic Corporation
    Inventors: Randy Yim, Christopher Neville