Abstract: A storage system is provided. The storage system includes a plurality of non-volatile memory modules a storage controller operatively coupled to the plurality of non-volatile memory modules, the storage controller comprising a processor. The process is to receive a set of data blocks to be stored in the plurality of non-volatile memory modules. The processor is further to program the set of data blocks at a first location of the plurality of non-volatile memory modules. The processor is further to determine whether a failure occurred while programming the set of data blocks in the plurality of non-volatile memory modules. The processor is further to reprogram a subset of the data blocks at a second location of the plurality of non-volatile memory modules, a number of blocks in the subset of data blocks based on durabilities of the set of data blocks, in response to determining that a failure occurred while programming the set of data blocks at the first location.

Abstract: Recovering corrupted data through speculative bitflip and cross-validation, including altering a first data portion stored in a storage device, wherein the first data portion contains an error; calculating a hash value using the altered first data portion; comparing the hash value calculated using the altered first data portion to a stored hash value for the first data portion; and based on the comparing, determining whether the altering corrects the error in the first data portion.

Abstract: A scheduling system for a memory controller is provided. The system includes a scheduler configurable to receive a plurality of operation requests from a plurality of masters. The scheduler is configurable to form a sequence of one or more phases from each of the operation requests. The scheduler is configurable to arbitrate the plurality of operation requests and the one or more phases through one or more configurable policies. The system includes a sequencer configurable to receive the one or more phases and communicate with at least two flash memory devices having differing types of flash memory device interfaces through a plurality of channels.

Abstract: A method for diagnosing memory, performed by a storage system, is provided. The method includes writing and reading through a communication channel to and from flash memory of each of a plurality of flash memory devices and a static random-access memory (SRAM) register of each of the plurality of flash memory devices. The method includes analyzing errors in read data from the reading through the communication channel, identifying types of errors among flash memory errors, SRAM register errors, and communication channel errors, based on the analyzing, and indicating at least one error and type of error from the read data.

Abstract: A method for diagnosing memory, performed by a storage system, is provided. The method includes writing and reading through a communication channel to and from flash memory of each of a plurality of flash memory devices and a static random-access memory (SRAM) register of each of the plurality of flash memory devices. The method includes analyzing errors in read data from the reading through the communication channel, identifying types of errors among flash memory errors, SRAM register errors, and communication channel errors, based on the analyzing, and indicating at least one error and type of error from the read data.

Abstract: A method for communicating with memory, performed by a memory controller, is provided. The method includes sampling reads from a plurality of memory devices and storing first calibration points in first buffers, based on the sampling, with at least one first calibration point and corresponding first buffer for each of the plurality of memory devices. The method includes sampling a read from a second memory device in background while performing a read from a first memory device using the first calibration point in the first buffer corresponding to the first memory device. The method includes storing a second calibration point in a second buffer, for the second memory device, based on the sampling in the background, with the first buffer for the second memory device having the first calibration point used for ongoing reads of the second memory device.

Abstract: A method for tracking and transitioning flash memory modes, performed by a storage system, is provided. The method includes tracking memory modes of a plurality of portions of flash memory, on a per portion basis, in a data structure in a first memory and determining, based on the data structure, whether the tracked memory mode of a portion of flash memory matches a memory mode for an I/O (input/output) command relating to the flash memory. The method includes sending at least one command to the flash memory to change the memory mode of the portion of flash memory, responsive to determining the tracked memory mode does not match the memory mode for the I/O command, and performing the I/O command with the memory mode of the portion of flash memory changed to match the memory mode for the I/O command.

Abstract: A caching system for increasing the operation concurrency between a cache module and a memory module by comparing received memory block identifiers, which correspond to texels needed for pixel composition, with memory block identifiers corresponding to texels locally stored within the cache module. If the received memory block identifiers match the memory block identifiers corresponding to locally cached texels, the system transmits these texels to a texture filter unit for pixel composition. If the received memory block identifiers do not match memory block identifiers corresponding to the locally cached texels, the system retrieves these texels from the memory module as fast as possible and then updates the cache module with the new texels. A plurality of first in, first out buffers are used to assist a controller module with synchronizing the transmission of the texels from the cache module and the overwriting of the texels received from the memory module into the cache module.