Patents by Inventor Ranen Chatterjee
Ranen Chatterjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12645497Abstract: A data processing system includes a runtime processor and a pool of reconfigurable data flow resources with memory units, busses, and arrays of physical configurable units. The runtime processor is operatively coupled to the pool of reconfigurable data flow resources and configured to load first and second configuration files for executing first and second user applications on first and second subsets of the arrays of physical configurable units and to assign first and second subsets of the memory units to the first and second user applications. The runtime processor starts execution of the first and second user applications on the first and second subsets of the arrays of physical configurable units, prevents the first user application from accessing the resources allocated to the second user application, and prevents the second user application from accessing resources allocated to the first user application.Type: GrantFiled: December 19, 2022Date of Patent: June 2, 2026Assignee: SambaNova Systems, Inc.Inventors: Ranen Chatterjee, Ravinder Kumar, Raghunath Shenbagam, Maran Wilson, Conrad Alexander Turlik, Arnav Goel, Arjun Sabnis, Yannan Chen
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Publication number: 20260140817Abstract: A fault management system, executed by one or more coarse grained reconfigurable processors (CGRPs), is provided to perform fault event notification. Before an application begins executing, the CGRPs receive data from the application, determine resources assigned to the application, and determine events associated with the resources. After the application begins executing, the CGRPs when receiving a notification of an event occurring using the fault management system determine that the event is associated with a particular resource and provide notification to the application of the occurrence of the event associated with the particular resource.Type: ApplicationFiled: April 15, 2025Publication date: May 21, 2026Applicant: SambaNova Systems, Inc.Inventors: Raghunath SHENBAGAM, Ranen CHATTERJEE, Anand MISRA, Jim LEWIS, Benjamin GLICK, Pushkar NANDKAR, Sruthi VEERAGANDHAM
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Publication number: 20260127041Abstract: A data processing system includes a pool of reconfigurable data flow resources having plurality of reconfigurable processors interconnected via a bus, controller, and runtime processor. The controller monitors ports of the bus connected to respective reconfigurable processors and generates hot-plug events in response to detecting disconnection or addition of reconfigurable processors. The runtime processor includes a kernel module with device abstraction module that presents all reconfigurable processors as a single virtual device file to user space, maintaining this unified presentation transparent to changes in the pool. Hot-plug events are transmitted as interrupts to a daemon module, which executes initialization of clocks, bus interfaces, and memory resources for added processors. The system supports distributed hot-plug controllers at each bus port communicating with controller service and driver.Type: ApplicationFiled: December 30, 2025Publication date: May 7, 2026Applicant: SambaNova Systems, Inc.Inventors: Anand MISRA, Conrad Alexander TURLIK, Maran WILSON, Anand VAYYALA, Raghu SHENBAGAM, Ranen CHATTERJEE, Pushkar Shridhar NANDKAR, Shivam RAIKUNDALIA
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Patent number: 12511174Abstract: A data processing system comprises a pool of reconfigurable data flow resources with arrays of physical configurable units, a controller, and a runtime processor. The controller is configured to generate a hot-plug event in response to detecting a removal of an unallocated array of physical configurable units from the pool of reconfigurable data flow resources. The runtime processor is configured to execute user applications on a subset of the arrays of physical configurable units and to receive the hot-plug event from the controller. The runtime processor is further configured to make the removed unallocated array of physical configurable units unavailable for subsequent allocations of subsequent virtual data flow resources and subsequent executions of subsequent user applications, while the subset of the arrays of physical configurable units continues the execution of the user applications.Type: GrantFiled: December 16, 2022Date of Patent: December 30, 2025Assignee: SambaNova Systems Inc.Inventors: Anand Misra, Conrad Alexander Turlik, Maran Wilson, Anand Vayyala, Raghu Shenbagam, Ranen Chatterjee, Pushkar Shridhar Nandkar, Shivam Raikundalia
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Patent number: 12287702Abstract: A fault management system (FMS) receives events indicating an issue with a component in the system and determines, based on an inventory database, the component associated with the events. The FMS creates, based at least in part on the events, an error report that includes: (i) an error type identifying a type of error described in the error report, (ii) a timestamp indicating when the error report was created, and (iii) a universal unique identifier (UUID) to uniquely identify the error report. The FMS determines, based at least in part on the error report, a policy associated with the events and classifies the events, based at least in part on the policy, as either a threshold event or a discrete event. The FMS performs one or more actions to address the events.Type: GrantFiled: February 3, 2023Date of Patent: April 29, 2025Assignee: SambaNova Systems, Inc.Inventors: Raghunath Shenbagam, Ranen Chatterjee, Anand Misra, Jim Lewis, Benjamin Glick, Pushkar Nandkar, Sruthi Veeragandham
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Publication number: 20240264896Abstract: A fault management system (FMS) receives events indicating an issue with a component in the system and determines, based on an inventory database, the component associated with the events. The FMS creates, based at least in part on the events, an error report that includes: (i) an error type identifying a type of error described in the error report, (ii) a timestamp indicating when the error report was created, and (iii) a universal unique identifier (UUID) to uniquely identify the error report. The FMS determines, based at least in part on the error report, a policy associated with the events and classifies the events, based at least in part on the policy, as either a threshold event or a discrete event. The FMS performs one or more actions to address the events.Type: ApplicationFiled: February 3, 2023Publication date: August 8, 2024Applicant: SambaNova Systems, Inc.Inventors: Raghunath SHENBAGAM, Ranen CHATTERJEE, Anand MISRA, Jim LEWIS, Benjamin GLICK, Pushkar NANDKAR, Sruthi VEERAGANDHAM
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Publication number: 20240202046Abstract: A data processing system comprises a pool of reconfigurable data flow resources with arrays of physical configurable units, a controller, and a runtime processor. The controller is configured to generate a hot-plug event in response to detecting a removal of an unallocated array of physical configurable units from the pool of reconfigurable data flow resources. The runtime processor is configured to execute user applications on a subset of the arrays of physical configurable units and to receive the hot-plug event from the controller. The runtime processor is further configured to make the removed unallocated array of physical configurable units unavailable for subsequent allocations of subsequent virtual data flow resources and subsequent executions of subsequent user applications, while the subset of the arrays of physical configurable units continues the execution of the user applications.Type: ApplicationFiled: December 16, 2022Publication date: June 20, 2024Applicant: SambaNova Systems, Inc.Inventors: Anand MISRA, Conrad Alexander TURLIK, Maran WILSON, Anand VAYYALA, Raghu SHENBAGAM, Ranen CHATTERJEE, Pushkar Shridhar NANDKAR, Shivam RAIKUNDALIA
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Patent number: 11886930Abstract: The technology disclosed relates to runtime execution of functions across reconfigurable processor. In particular, the technology disclosed relates to a runtime logic that is configured to execute a first set of functions in a plurality of functions and/or data therefor on a first reconfigurable processor, and a second set of functions in the plurality of functions and/or data therefor on additional reconfigurable processors. Functions in the second set of functions and/or the data therefor are transmitted to the additional reconfigurable processors using one or more of a first reconfigurable processor-to-additional reconfigurable processors buffers, and results of executing the functions and/or the data therefor on the additional reconfigurable processors are transmitted to the first reconfigurable processor using one or more of additional reconfigurable processors-to-first reconfigurable processor buffers.Type: GrantFiled: November 9, 2021Date of Patent: January 30, 2024Assignee: SambaNova Systems, Inc.Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
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Patent number: 11886931Abstract: The technology disclosed relates to inter-node execution of configuration files on reconfigurable processors using network interface controller (NIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and application data for applications using a first reconfigurable processor connected to a first host, and a second reconfigurable processor connected to a second host. The first reconfigurable processor is configured to push input data for the applications in a first plurality of buffers. The first host is configured to cause a first network interface controller (NIC) to stream the input data to a second plurality of buffers from the first plurality of buffers. The second host is configured to cause a second NIC to stream the input data to the second reconfigurable processor from the second plurality of buffers.Type: GrantFiled: November 9, 2021Date of Patent: January 30, 2024Assignee: SambaNova Systems, Inc.Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
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Patent number: 11782729Abstract: A data processing system comprises a pool of reconfigurable data flow resources and a runtime processor. The pool of reconfigurable data flow resources includes arrays of physical configurable units and memory. The runtime processor includes logic to receive a plurality of configuration files for user applications. The configuration files include configurations of virtual data flow resources required to execute the user applications. The runtime processor also includes logic to allocate physical configurable units and memory in the pool of reconfigurable data flow resources to the virtual data flow resources and load the configuration files to the allocated physical configurable units. The runtime processor further includes logic to execute the user applications using the allocated physical configurable units and memory.Type: GrantFiled: August 18, 2020Date of Patent: October 10, 2023Assignee: SambaNova Systems, Inc.Inventors: Gregory Frederick Grohoski, Manish K. Shah, Raghu Prabhakar, Mark Luttrell, Ravinder Kumar, Kin Hing Leung, Ranen Chatterjee, Sumti Jairath, David Alan Koeplinger, Ram Sivaramakrishnan, Matthew Thomas Grimm
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Publication number: 20230205585Abstract: A data processing system includes a runtime processor and a pool of reconfigurable data flow resources with memory units, busses, and arrays of physical configurable units. The runtime processor is operatively coupled to the pool of reconfigurable data flow resources and configured to load first and second configuration files for executing first and second user applications on first and second subsets of the arrays of physical configurable units and to assign first and second subsets of the memory units to the first and second user applications. The runtime processor starts execution of the first and second user applications on the first and second subsets of the arrays of physical configurable units, prevents the first user application from accessing the resources allocated to the second user application, and prevents the second user application from accessing resources allocated to the first user application.Type: ApplicationFiled: December 19, 2022Publication date: June 29, 2023Applicant: SambaNova Systems, Inc.Inventors: Ranen CHATTERJEE, Ravinder KUMAR, Raghunath SHENBAGAM, Maran WILSON, Conrad Alexander TURLIK, Arnav GOEL, Arjun SABNIS, Yannan CHEN
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Patent number: 11625284Abstract: The technology disclosed relates to inter-node execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor on a first node, and a second host processor on a second node. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second host processor using one or more SmartNIC buffers.Type: GrantFiled: November 9, 2021Date of Patent: April 11, 2023Assignee: SambaNova Systems, Inc.Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
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Patent number: 11625283Abstract: The technology disclosed relates to inter-processor execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor and a second reconfigurable processor. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second reconfigurable processor using one or more SmartNIC buffers.Type: GrantFiled: November 9, 2021Date of Patent: April 11, 2023Assignee: SambaNova Systems, Inc.Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
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Patent number: 11609798Abstract: The technology disclosed relates to runtime execution of configuration files on reconfigurable processors with varying configuration granularity. In particular, the technology disclosed relates to a runtime logic that is configured to receive a set of configuration files for an application, and load and execute a first subset of configuration files in the set of configuration files and associated application data on a first reconfigurable processor. The first reconfigurable processor has a first level of configurable granularity. The runtime logic is further configured to load and execute a second subset of configuration files in the set of configuration files and associated application data on a second reconfigurable processor. The second reconfigurable processor has a second level of configurable granularity that is different from the first level of configurable granularity.Type: GrantFiled: November 9, 2021Date of Patent: March 21, 2023Assignee: SambaNova Systems, Inc.Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
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Patent number: 11487694Abstract: A data processing system comprises a pool of reconfigurable data flow resources with arrays of physical configurable units, a controller, and a runtime processor. The controller is configured to generate a hot-plug event in response to detecting a removal of an unallocated array of physical configurable units from the pool of reconfigurable data flow resources. The runtime processor is configured to execute user applications on a subset of the arrays of physical configurable units and to receive the hot-plug event from the controller. The runtime processor is further configured to make the removed unallocated array of physical configurable units unavailable for subsequent allocations of subsequent virtual data flow resources and subsequent executions of subsequent user applications, while the subset of the arrays of physical configurable units continues the execution of the user applications.Type: GrantFiled: December 17, 2021Date of Patent: November 1, 2022Assignee: SambaNova Systems, Inc.Inventors: Anand Misra, Conrad Alexander Turlik, Maran Wilson, Anand Vayyala, Raghu Shenbagam, Ranen Chatterjee, Pushkar Shridhar Nandkar, Shivam Raikundalia
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Publication number: 20220197711Abstract: The technology disclosed relates to runtime execution of functions across reconfigurable processor. In particular, the technology disclosed relates to a runtime logic that is configured to execute a first set of functions in a plurality of functions and/or data therefor on a first reconfigurable processor, and a second set of functions in the plurality of functions and/or data therefor on additional reconfigurable processors. Functions in the second set of functions and/or the data therefor are transmitted to the additional reconfigurable processors using one or more of a first reconfigurable processor-to-additional reconfigurable processors buffers, and results of executing the functions and/or the data therefor on the additional reconfigurable processors are transmitted to the first reconfigurable processor using one or more of additional reconfigurable processors-to-first reconfigurable processor buffers.Type: ApplicationFiled: November 9, 2021Publication date: June 23, 2022Applicant: SambaNova Systems, Inc.Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
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Publication number: 20220197713Abstract: The technology disclosed relates to inter-node execution of configuration files on reconfigurable processors using network interface controller (NIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and application data for applications using a first reconfigurable processor connected to a first host, and a second reconfigurable processor connected to a second host. The first reconfigurable processor is configured to push input data for the applications in a first plurality of buffers. The first host is configured to cause a first network interface controller (NIC) to stream the input data to a second plurality of buffers from the first plurality of buffers. The second host is configured to cause a second NIC to stream the input data to the second reconfigurable processor from the second plurality of buffers.Type: ApplicationFiled: November 9, 2021Publication date: June 23, 2022Applicant: SambaNova Systems, Inc.Inventors: Ram SIVARAMAKRISHNAN, Sumti JAIRATH, Emre Ali BURHAN, Manish K. SHAH, Raghu PRABHAKAR, Ravinder KUMAR, Arnav GOEL, Ranen CHATTERJEE, Gregory Frederick GROHOSKI, Kin Hing LEUNG, Dawei HUANG, Manoj UNNIKRISHNAN, Martin Russell RAUMANN, Bandish B. SHAH
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Publication number: 20220197709Abstract: The technology disclosed relates to runtime execution of configuration files on reconfigurable processors with varying configuration granularity. In particular, the technology disclosed relates to a runtime logic that is configured to receive a set of configuration files for an application, and load and execute a first subset of configuration files in the set of configuration files and associated application data on a first reconfigurable processor. The first reconfigurable processor has a first level of configurable granularity. The runtime logic is further configured to load and execute a second subset of configuration files in the set of configuration files and associated application data on a second reconfigurable processor. The second reconfigurable processor has a second level of configurable granularity that is different from the first level of configurable granularity.Type: ApplicationFiled: November 9, 2021Publication date: June 23, 2022Applicant: SambaNova Systems, Inc.Inventors: Ram SIVARAMAKRISHNAN, Sumti JAIRATH, Emre Ali BURHAN, Manish K. SHAH, Raghu PRABHAKAR, Ravinder KUMAR, Arnav GOEL, Ranen CHATTERJEE, Gregory Frederick GROHOSKI, Kin Hing LEUNG, Dawei HUANG, Manoj UNNIKRISHNAN, Martin Russell RAUMANN, Bandish B. SHAH
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Publication number: 20220197712Abstract: The technology disclosed relates to inter-node execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor on a first node, and a second host processor on a second node. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second host processor using one or more SmartNIC buffers.Type: ApplicationFiled: November 9, 2021Publication date: June 23, 2022Applicant: SambaNova Systems, Inc.Inventors: Ram SIVARAMAKRISHNAN, Sumti JAIRATH, Emre Ali BURHAN, Manish K. SHAH, Raghu PRABHAKAR, Ravinder KUMAR, Arnav GOEL, Ranen CHATTERJEE, Gregory Frederick GROHOSKI, Kin Hing LEUNG, Dawei HUANG, Manoj UNNIKRISHNAN, Martin Russell RAUMANN, Bandish B. SHAH
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Publication number: 20220197710Abstract: The technology disclosed relates to inter-processor execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor and a second reconfigurable processor. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second reconfigurable processor using one or more SmartNIC buffers.Type: ApplicationFiled: November 9, 2021Publication date: June 23, 2022Applicant: SambaNova Systems, Inc.Inventors: Ram SIVARAMAKRISHNAN, Sumti JAIRATH, Emre Ali BURHAN, Manish K. SHAH, Raghu PRABHAKAR, Ravinder KUMAR, Arnav GOEL, Ranen CHATTERJEE, Gregory Frederick GROHOSKI, Kin Hing LEUNG, Dawei HUANG, Manoj UNNIKRISHNAN, Martin Russell RAUMANN, Bandish B. SHAH