Patents by Inventor Ranen Chatterjee

Ranen Chatterjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11886931
    Abstract: The technology disclosed relates to inter-node execution of configuration files on reconfigurable processors using network interface controller (NIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and application data for applications using a first reconfigurable processor connected to a first host, and a second reconfigurable processor connected to a second host. The first reconfigurable processor is configured to push input data for the applications in a first plurality of buffers. The first host is configured to cause a first network interface controller (NIC) to stream the input data to a second plurality of buffers from the first plurality of buffers. The second host is configured to cause a second NIC to stream the input data to the second reconfigurable processor from the second plurality of buffers.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: January 30, 2024
    Assignee: SambaNova Systems, Inc.
    Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
  • Patent number: 11886930
    Abstract: The technology disclosed relates to runtime execution of functions across reconfigurable processor. In particular, the technology disclosed relates to a runtime logic that is configured to execute a first set of functions in a plurality of functions and/or data therefor on a first reconfigurable processor, and a second set of functions in the plurality of functions and/or data therefor on additional reconfigurable processors. Functions in the second set of functions and/or the data therefor are transmitted to the additional reconfigurable processors using one or more of a first reconfigurable processor-to-additional reconfigurable processors buffers, and results of executing the functions and/or the data therefor on the additional reconfigurable processors are transmitted to the first reconfigurable processor using one or more of additional reconfigurable processors-to-first reconfigurable processor buffers.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: January 30, 2024
    Assignee: SambaNova Systems, Inc.
    Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
  • Patent number: 11782729
    Abstract: A data processing system comprises a pool of reconfigurable data flow resources and a runtime processor. The pool of reconfigurable data flow resources includes arrays of physical configurable units and memory. The runtime processor includes logic to receive a plurality of configuration files for user applications. The configuration files include configurations of virtual data flow resources required to execute the user applications. The runtime processor also includes logic to allocate physical configurable units and memory in the pool of reconfigurable data flow resources to the virtual data flow resources and load the configuration files to the allocated physical configurable units. The runtime processor further includes logic to execute the user applications using the allocated physical configurable units and memory.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: October 10, 2023
    Assignee: SambaNova Systems, Inc.
    Inventors: Gregory Frederick Grohoski, Manish K. Shah, Raghu Prabhakar, Mark Luttrell, Ravinder Kumar, Kin Hing Leung, Ranen Chatterjee, Sumti Jairath, David Alan Koeplinger, Ram Sivaramakrishnan, Matthew Thomas Grimm
  • Publication number: 20230205585
    Abstract: A data processing system includes a runtime processor and a pool of reconfigurable data flow resources with memory units, busses, and arrays of physical configurable units. The runtime processor is operatively coupled to the pool of reconfigurable data flow resources and configured to load first and second configuration files for executing first and second user applications on first and second subsets of the arrays of physical configurable units and to assign first and second subsets of the memory units to the first and second user applications. The runtime processor starts execution of the first and second user applications on the first and second subsets of the arrays of physical configurable units, prevents the first user application from accessing the resources allocated to the second user application, and prevents the second user application from accessing resources allocated to the first user application.
    Type: Application
    Filed: December 19, 2022
    Publication date: June 29, 2023
    Applicant: SambaNova Systems, Inc.
    Inventors: Ranen CHATTERJEE, Ravinder KUMAR, Raghunath SHENBAGAM, Maran WILSON, Conrad Alexander TURLIK, Arnav GOEL, Arjun SABNIS, Yannan CHEN
  • Patent number: 11625283
    Abstract: The technology disclosed relates to inter-processor execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor and a second reconfigurable processor. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second reconfigurable processor using one or more SmartNIC buffers.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: April 11, 2023
    Assignee: SambaNova Systems, Inc.
    Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
  • Patent number: 11625284
    Abstract: The technology disclosed relates to inter-node execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor on a first node, and a second host processor on a second node. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second host processor using one or more SmartNIC buffers.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: April 11, 2023
    Assignee: SambaNova Systems, Inc.
    Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
  • Patent number: 11609798
    Abstract: The technology disclosed relates to runtime execution of configuration files on reconfigurable processors with varying configuration granularity. In particular, the technology disclosed relates to a runtime logic that is configured to receive a set of configuration files for an application, and load and execute a first subset of configuration files in the set of configuration files and associated application data on a first reconfigurable processor. The first reconfigurable processor has a first level of configurable granularity. The runtime logic is further configured to load and execute a second subset of configuration files in the set of configuration files and associated application data on a second reconfigurable processor. The second reconfigurable processor has a second level of configurable granularity that is different from the first level of configurable granularity.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: March 21, 2023
    Assignee: SambaNova Systems, Inc.
    Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
  • Patent number: 11487694
    Abstract: A data processing system comprises a pool of reconfigurable data flow resources with arrays of physical configurable units, a controller, and a runtime processor. The controller is configured to generate a hot-plug event in response to detecting a removal of an unallocated array of physical configurable units from the pool of reconfigurable data flow resources. The runtime processor is configured to execute user applications on a subset of the arrays of physical configurable units and to receive the hot-plug event from the controller. The runtime processor is further configured to make the removed unallocated array of physical configurable units unavailable for subsequent allocations of subsequent virtual data flow resources and subsequent executions of subsequent user applications, while the subset of the arrays of physical configurable units continues the execution of the user applications.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: November 1, 2022
    Assignee: SambaNova Systems, Inc.
    Inventors: Anand Misra, Conrad Alexander Turlik, Maran Wilson, Anand Vayyala, Raghu Shenbagam, Ranen Chatterjee, Pushkar Shridhar Nandkar, Shivam Raikundalia
  • Publication number: 20220197709
    Abstract: The technology disclosed relates to runtime execution of configuration files on reconfigurable processors with varying configuration granularity. In particular, the technology disclosed relates to a runtime logic that is configured to receive a set of configuration files for an application, and load and execute a first subset of configuration files in the set of configuration files and associated application data on a first reconfigurable processor. The first reconfigurable processor has a first level of configurable granularity. The runtime logic is further configured to load and execute a second subset of configuration files in the set of configuration files and associated application data on a second reconfigurable processor. The second reconfigurable processor has a second level of configurable granularity that is different from the first level of configurable granularity.
    Type: Application
    Filed: November 9, 2021
    Publication date: June 23, 2022
    Applicant: SambaNova Systems, Inc.
    Inventors: Ram SIVARAMAKRISHNAN, Sumti JAIRATH, Emre Ali BURHAN, Manish K. SHAH, Raghu PRABHAKAR, Ravinder KUMAR, Arnav GOEL, Ranen CHATTERJEE, Gregory Frederick GROHOSKI, Kin Hing LEUNG, Dawei HUANG, Manoj UNNIKRISHNAN, Martin Russell RAUMANN, Bandish B. SHAH
  • Publication number: 20220197713
    Abstract: The technology disclosed relates to inter-node execution of configuration files on reconfigurable processors using network interface controller (NIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and application data for applications using a first reconfigurable processor connected to a first host, and a second reconfigurable processor connected to a second host. The first reconfigurable processor is configured to push input data for the applications in a first plurality of buffers. The first host is configured to cause a first network interface controller (NIC) to stream the input data to a second plurality of buffers from the first plurality of buffers. The second host is configured to cause a second NIC to stream the input data to the second reconfigurable processor from the second plurality of buffers.
    Type: Application
    Filed: November 9, 2021
    Publication date: June 23, 2022
    Applicant: SambaNova Systems, Inc.
    Inventors: Ram SIVARAMAKRISHNAN, Sumti JAIRATH, Emre Ali BURHAN, Manish K. SHAH, Raghu PRABHAKAR, Ravinder KUMAR, Arnav GOEL, Ranen CHATTERJEE, Gregory Frederick GROHOSKI, Kin Hing LEUNG, Dawei HUANG, Manoj UNNIKRISHNAN, Martin Russell RAUMANN, Bandish B. SHAH
  • Publication number: 20220197711
    Abstract: The technology disclosed relates to runtime execution of functions across reconfigurable processor. In particular, the technology disclosed relates to a runtime logic that is configured to execute a first set of functions in a plurality of functions and/or data therefor on a first reconfigurable processor, and a second set of functions in the plurality of functions and/or data therefor on additional reconfigurable processors. Functions in the second set of functions and/or the data therefor are transmitted to the additional reconfigurable processors using one or more of a first reconfigurable processor-to-additional reconfigurable processors buffers, and results of executing the functions and/or the data therefor on the additional reconfigurable processors are transmitted to the first reconfigurable processor using one or more of additional reconfigurable processors-to-first reconfigurable processor buffers.
    Type: Application
    Filed: November 9, 2021
    Publication date: June 23, 2022
    Applicant: SambaNova Systems, Inc.
    Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
  • Publication number: 20220197710
    Abstract: The technology disclosed relates to inter-processor execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor and a second reconfigurable processor. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second reconfigurable processor using one or more SmartNIC buffers.
    Type: Application
    Filed: November 9, 2021
    Publication date: June 23, 2022
    Applicant: SambaNova Systems, Inc.
    Inventors: Ram SIVARAMAKRISHNAN, Sumti JAIRATH, Emre Ali BURHAN, Manish K. SHAH, Raghu PRABHAKAR, Ravinder KUMAR, Arnav GOEL, Ranen CHATTERJEE, Gregory Frederick GROHOSKI, Kin Hing LEUNG, Dawei HUANG, Manoj UNNIKRISHNAN, Martin Russell RAUMANN, Bandish B. SHAH
  • Publication number: 20220197712
    Abstract: The technology disclosed relates to inter-node execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor on a first node, and a second host processor on a second node. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second host processor using one or more SmartNIC buffers.
    Type: Application
    Filed: November 9, 2021
    Publication date: June 23, 2022
    Applicant: SambaNova Systems, Inc.
    Inventors: Ram SIVARAMAKRISHNAN, Sumti JAIRATH, Emre Ali BURHAN, Manish K. SHAH, Raghu PRABHAKAR, Ravinder KUMAR, Arnav GOEL, Ranen CHATTERJEE, Gregory Frederick GROHOSKI, Kin Hing LEUNG, Dawei HUANG, Manoj UNNIKRISHNAN, Martin Russell RAUMANN, Bandish B. SHAH
  • Publication number: 20220058034
    Abstract: A data processing system comprises a pool of reconfigurable data flow resources and a runtime processor. The pool of reconfigurable data flow resources includes arrays of physical configurable units and memory. The runtime processor includes logic to receive a plurality of configuration files for user applications. The configuration files include configurations of virtual data flow resources required to execute the user applications. The runtime processor also includes logic to allocate physical configurable units and memory in the pool of reconfigurable data flow resources to the virtual data flow resources and load the configuration files to the allocated physical configurable units. The runtime processor further includes logic to execute the user applications using the allocated physical configurable units and memory.
    Type: Application
    Filed: August 18, 2020
    Publication date: February 24, 2022
    Applicant: SambaNova Systems, Inc.
    Inventors: Gregory Frederick GROHOSKI, Manish K. SHAH, Raghu PRABHAKAR, Mark LUTTRELL, Ravinder KUMAR, Kin Hing LEUNG, Ranen CHATTERJEE, Sumti JAIRATH, David Alan KOEPLINGER, Ram SIVARAMAKRISHNAN, Matthew Thomas GRIMM
  • Patent number: 11182264
    Abstract: A data processing system comprises a plurality of reconfigurable processors including a first reconfigurable processor and additional reconfigurable processors, a plurality of buffers in a shared memory accessible to the first reconfigurable processor and the additional reconfigurable processors, and runtime logic configured to execute one or more configuration files for applications using the first reconfigurable processor and the additional reconfigurable processors. Execution of the configuration files includes receiving data from the first reconfigurable processor and providing the data to at least one of the additional reconfigurable processors, and receiving data from the at least one of the additional reconfigurable processors and providing the data to the first reconfigurable processor.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: November 23, 2021
    Assignee: SambaNova Systems, Inc.
    Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
  • Patent number: 11182221
    Abstract: The technology disclosed relates to buffer-based inter-node streaming of configuration data over a network fabric. In particular, the technology disclosed relates to a runtime processor configured to load and execute a first subset of configuration files in a set of configuration files on a first reconfigurable processor operatively coupled to a first processing node, load and execute a second subset of configuration files in the set of configuration files on a second reconfigurable processor operatively coupled to a second processing node, and use a first plurality of buffers operatively coupled to the first processing node, and a second plurality of buffers operatively coupled to the second processing node to stream data between the first reconfigurable processor and the second reconfigurable processor to load and execute the first subset of configuration files and the second subset of configuration files.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: November 23, 2021
    Assignee: SambaNova Systems, Inc.
    Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
  • Patent number: 7533210
    Abstract: A Compact Peripheral Component Interconnect (CPCI) system is provided that allows an Intelligent Platform Management Interface (IPMI) controller to be virtualized across many interested client entities. The system may include one or more interfaces that are provided by a virtualizing entity to allow a client application to obtain a handle to a virtual micro-controller, interfaces that are provided to reserve exclusive rights on certain IPMI commands on a particular virtual controller, and/or interfaces that are provided to request for a particular type of asynchronous message received on an IPMI micro-controller. In addition, the system may provide a reservation of IPMI sequence numbers over a virtual client and a usage of the IPMI sequence numbers to decide the intended virtual controller. The system may also be used to perform the many independent management tasks.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: May 12, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Ranen Chatterjee, Srinivasa Babu Venkatachalam
  • Patent number: 7103704
    Abstract: A system and method is provided that allows an Intelligent Platform Management Interface (IPMI) controller (or another micro-controller that is not a dedicated I2C controller) to control various Inter Integrated Circuit (I2C) slave devices having I2C slave drivers without any modification of the I2C slave drivers on the I2C slave devices. The I2C slave devices can be managed without an external and/or a dedicated I2C master controller. In one embodiment, a translation module is provided to an IPMI micro-controller that can represent I2C interface to I2C device drivers. In another embodiment, the translation module can represent an interface for an IPMI controller to I2C device drivers located in one or more I2C devices and/or I2C controllers.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: September 5, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: Ranen Chatterjee
  • Publication number: 20050091438
    Abstract: A system and method is provided that allows an Intelligent Platform Management Interface (IPMI) controller (or another micro-controller that is not a dedicated I2C controller) to control various Inter Integrated Circuit (I2C) slave devices having I2C slave drivers without any modification of the I2C slave drivers on the I2C slave devices. The I2C slave devices can be managed without an external and/or a dedicated I2C master controller. In one embodiment, a translation module is provided to an IPMI micro-controller that can represent I2C interface to I2C device drivers. In another embodiment, the translation module can represent an interface for an IPMI controller to I2C device drivers located in one or more I2C devices and/or I2C controllers.
    Type: Application
    Filed: October 24, 2003
    Publication date: April 28, 2005
    Inventor: Ranen Chatterjee
  • Publication number: 20040083356
    Abstract: A Compact Peripheral Component Interconnect (CPCI) system is provided that allows an Intelligent Platform Management Interface (IPMI) controller to be virtualized across many interested client entities. The system may include one or more interfaces that are provided by a virtualizing entity to allow a client application to obtain a handle to a virtual micro-controller, interfaces that are provided to reserve exclusive rights on certain IPMI commands on a particular virtual controller, and/or interfaces that are provided to request for a particular type of asynchronous message received on an IPMI micro-controller. In addition, the system may provide a reservation of IPMI sequence numbers over a virtual client and a usage of the IPMI sequence numbers to decide the intended virtual controller. The system may also be used to perform the many independent management tasks of the system without any explicit correlation between them while using the resources of the single IPMI micro-controller.
    Type: Application
    Filed: October 21, 2003
    Publication date: April 29, 2004
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Ranen Chatterjee, Srinivasa Babu Venkatachalam