Abstract: Routing layers, e.g., back-end of line (BEOL) routing layers, of a semiconductor device are disclosed. Unlike conventional routing layers, the proposed routing layers include mixed pitch track patterns. As such, routing layers with reduced resistance-capacitance (RC) and low routing cost may be achieved.

Abstract: Routing layers, e.g., back-end of line (BEOL) routing layers, of a semiconductor device are disclosed. Unlike conventional routing layers, the proposed routing layers include mixed pitch track patterns. As such, routing layers with reduced resistance-capacitance (RC) and low routing cost may be achieved.

Abstract: In certain aspects of the disclosure, a chip includes a power distribution network for distributing power to device on the chip. The power distribution network includes a first portion formed from a first metal layer on the chip, a second portion formed from a second metal layer on the chip, and vias interconnecting the first and second portions of the power distribution network, wherein the vias include a first plurality of vias and a second plurality of vias, each one of the first plurality of vias has a first via size, and each one of the second plurality of vias has a second via size. The devices on the chip are electrically coupled to the first portion of the power distribution network.