Patents by Inventor Rangarajan Jagannathan
Rangarajan Jagannathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240100713Abstract: Embodiments described herein generally relate to equipment used in the manufacturing of electronic devices, and more particularly, to a cleaning system, cleaning system hardware and related methods which may be used to transport and clean the surface of a substrate. According to one embodiment, a blade handling assembly for handling a substrate in a cleaning system includes a gripping assembly including a pair of gripping blades, the blades operable with a gripping actuator to hold a substrate at its edges. The assembly includes a first blade actuator for moving the gripping assembly and substrate between a horizontal and a vertical orientation utilizing a first axis. The assembly includes a second blade actuator for moving the vertically oriented gripping assembly and substrate 180 degrees utilizing a second axis, thereby causing the substrate to face an opposite direction.Type: ApplicationFiled: September 11, 2023Publication date: March 28, 2024Inventors: Jagan RANGARAJAN, Edward GOLUBOVSKY, Edwin VELAZQUEZ, Adrian S. BLANK, Steven M. ZUNIGA, Balasubramaniam C. JAGANNATHAN
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Publication number: 20240100714Abstract: Embodiments described herein generally relate to equipment used in the manufacturing of electronic devices, and more particularly, to a cleaning system, cleaning system hardware and related methods which may be used to transport and clean the surface of a substrate. According to one embodiment, a substrate cleaning unit may include a pre-clean chamber that performs a pre-clean process on a substrate with the substrate in a horizontal orientation. The unit may also include a first cleaning chamber that performs a first cleaning process on the substrate with the substrate in a vertical orientation. The unit may also include a second cleaning chamber. The unit may also include an integrated cleaning and drying chamber that performs a cleaning and drying process on the substrate in the horizontal orientation. A substrate handler may transfer the substrate between the chambers. The first and second cleaning chambers may be positioned below the pre-clean chamber.Type: ApplicationFiled: November 20, 2023Publication date: March 28, 2024Inventors: Jagan RANGARAJAN, Edward GOLUBOVSKY, Edwin VALAZQUEZ, Adrian S. BLANK, Steven M. ZUNIGA, Balasubramaniam C. JAGANNATHAN
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Patent number: 11199769Abstract: A method of processing a trench, via, hole, recess, void, or other feature that extends a depth into a substrate to a base or bottom and has an opening by irradiation with an accelerated neutral beam derived from an accelerated gas cluster ion beam for processing materials at the base or bottom of the opening.Type: GrantFiled: June 14, 2018Date of Patent: December 14, 2021Inventors: Sean R. Kirkpatrick, Rangarajan Jagannathan
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Patent number: 10882842Abstract: The present invention concerns pyridinium compounds, a synthesis method for their preparation, metal or metal alloy plating baths containing said pyridinium compounds and a method for use of said metal or metal alloy plating baths. The plating baths are particularly suitable for use in filling of recessed structures in the electronics and semiconductor industry including dual damascene applications.Type: GrantFiled: January 26, 2018Date of Patent: January 5, 2021Assignee: Atotech Deutschland GmbHInventors: Rangarajan Jagannathan, James Adolf, Jun Wu, Lars Kohlmann, Heiko Brunner
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Publication number: 20200231565Abstract: The present invention concerns pyridinium compounds, a synthesis method for their preparation, metal or metal alloy plating baths containing said pyridinium compounds and a method for use of said metal or metal alloy plating baths. The plating baths are particularly suitable for use in filling of recessed structures in the electronics and semiconductor industry including dual damascene applications.Type: ApplicationFiled: January 26, 2018Publication date: July 23, 2020Inventors: Rangarajan JAGANNATHAN, James ADOLF, Jun WU, Lars KOHLMANN, Heiko BRUNNER
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Publication number: 20180299771Abstract: A method of processing a trench, via, hole, recess, void, or other feature that extends a depth into a substrate to a base or bottom and has an opening by irradiation with an accelerated neutral beam derived from an accelerated gas cluster ion beam for processing materials at the base or bottom of the opening.Type: ApplicationFiled: June 14, 2018Publication date: October 18, 2018Applicant: Exogenesis CorporationInventors: Sean R. Kirkpatrick, Rangarajan Jagannathan
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Patent number: 8536630Abstract: In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.Type: GrantFiled: November 21, 2011Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: John C. Arnold, Xuefeng Hua, Rangarajan Jagannathan, Stefan Schmitz
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Publication number: 20120061684Abstract: In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.Type: ApplicationFiled: November 21, 2011Publication date: March 15, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John C. Arnold, Xuefeng Hua, Rangarajan Jagannathan, Stefan Schmitz
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Patent number: 8084329Abstract: In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.Type: GrantFiled: January 26, 2010Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: John C. Arnold, Xuefeng Hua, Rangarajan Jagannathan, Stefan Schmitz
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Patent number: 7859013Abstract: Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.Type: GrantFiled: December 13, 2007Date of Patent: December 28, 2010Assignee: International Business Machines CorporationInventors: Huajie Chen, Judson R. Holt, Rangarajan Jagannathan, Wesley C. Natzle, Michael R. Sievers, Richard S. Wise
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Publication number: 20100187579Abstract: In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.Type: ApplicationFiled: January 26, 2010Publication date: July 29, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: JOHN C. ARNOLD, XUEFENG HUA, RANGARAJAN JAGANNATHAN, STEFAN SCHMITZ
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Patent number: 7595010Abstract: Adding at least one non-silicon precursor (such as a germanium precursor, a carbon precursor, etc.) during formation of a silicon nitride, silicon oxide, silicon oxynitride or silicon carbide film improves the deposition rate and/or makes possible tuning of properties of the film, such as tuning of the stress of the film. Also, in a doped silicon oxide or doped silicon nitride or other doped structure, the presence of the dopant may be used for measuring a signal associated with the dopant, as an etch-stop or otherwise for achieving control during etching.Type: GrantFiled: October 26, 2007Date of Patent: September 29, 2009Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Judson Holt, Kevin K. Chan, Sadanand V. Deshpande, Rangarajan Jagannathan
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Patent number: 7435652Abstract: Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks.Type: GrantFiled: March 30, 2007Date of Patent: October 14, 2008Assignee: International Business Machines CorporationInventors: Tze-chiang Chen, Bruce B. Doris, Rangarajan Jagannathan, Hongwen Yan, Qingyun Yang, Ying Zhang
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Publication number: 20080242070Abstract: Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tze-chiang Chen, Bruce B. Doris, Rangarajan Jagannathan, Hongwen Yan, Qingyun Yang, Ying Zhang
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Patent number: 7384835Abstract: Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.Type: GrantFiled: May 25, 2006Date of Patent: June 10, 2008Assignee: International Business Machines CorporationInventors: Huajie Chen, Judson R Holt, Rangarajan Jagannathan, Wesley C Natzle, Michael R Sievers, Richard S Wise
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Publication number: 20080093629Abstract: Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.Type: ApplicationFiled: December 13, 2007Publication date: April 24, 2008Applicant: International Business Machines CorporationInventors: Huajie Chen, Judson Holt, Rangarajan Jagannathan, Wesley Natzle, Michael Sievers, Richard Wise
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Patent number: 7361611Abstract: Adding at least one non-silicon precursor (such as a germanium precursor, a carbon precursor, etc.) during formation of a silicon nitride, silicon oxide, silicon oxynitride or silicon carbide film improves the deposition rate and/or makes possible tuning of properties of the film, such as tuning of the stress of the film. Also, in a doped silicon oxide or doped silicon nitride or other doped structure, the presence of the dopant may be used for measuring a signal associated with the dopant, as an etch-stop or otherwise for achieving control during etching.Type: GrantFiled: February 8, 2006Date of Patent: April 22, 2008Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Judson Holt, Kevin K. Chan, Sadanand V. Deshpande, Rangarajan Jagannathan
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Publication number: 20080054228Abstract: Adding at least one non-silicon precursor (such as a germanium precursor, a carbon precursor, etc.) during formation of a silicon nitride, silicon oxide, silicon oxynitride or silicon carbide film improves the deposition rate and/or makes possible tuning of properties of the film, such as tuning of the stress of the film. Also, in a doped silicon oxide or doped silicon nitride or other doped structure, the presence of the dopant may be used for measuring a signal associated with the dopant, as an etch-stop or otherwise for achieving control during etching.Type: ApplicationFiled: October 26, 2007Publication date: March 6, 2008Inventors: Ashima Chakravarti, Judson Holt, Kevin Chan, Sadanand Deshpande, Rangarajan Jagannathan
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Publication number: 20070275510Abstract: Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.Type: ApplicationFiled: May 25, 2006Publication date: November 29, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huajie Chen, Judson R. Holt, Rangarajan Jagannathan, Wesley C. Natzle, Michael R. Sievers, Richard S. Wise
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Publication number: 20060237846Abstract: When forming a silicon nitride film from a nitrogen precursor, using a silicon precursor combination rather than a single silane precursor advantageously increases the deposition rate. For example, adding silane during formation of a silicon nitride film made using BTBAS and ammonia improves (increases) the deposition rate while still yielding a film with a favorably high stress.Type: ApplicationFiled: July 5, 2006Publication date: October 26, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ashima Chakravarti, Shawn Smith, Dominic Schepis, Rangarajan Jagannathan, Anita Madan