Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of segmenting the target pattern into a plurality of patches; identifying critical features within each patch which violate minimum spacing requirements; generating a critical group graph for each of the plurality of patches having critical features, where the critical group graph of a given patch defines a coloring scheme of the critical features within the given patch, and the critical group graph identifies critical features extending into adjacent patches to the given patch; generating a global critical group graph for the target pattern, where the global critical group graph includes the critical group graphs of each of the plurality of patches, and an identification of the features extending into adjacent patches; and coloring the target pattern based on the coloring scheme defined by the global critical group graph.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A novel compression method uses bitmaps to reduce the memory storage requirement of routing table information to about 3 MB. The data structure can be used for both route lookup and update. It does not require a separate data structure to be used for route update. A fast route lookup method is also disclosed. An efficient update method supports incremental route update. Through configuring a processor properly and developing a few customized instructions specifically for route lookup, the system can achieve more than 10 million lookups per second (MLPS) at 200 MHz. Using a configurable processor for route lookup/update provides more flexibility and extensibility which supports different data structures and lookup/update methods to meet application specific needs. The data structure and lookup method can be implemented in pure hardware in a pipelined fashion to achieve approximately 100 MLPS.

Abstract: Polyolefins, especially polypropylene, can be made flame retardant by the incorporation therein of a synergistic mixture of a selected hindered amine substituted by an alkoxy, cycloalkoxy or hydroxyalkoxy moiety and a selected organic or inorganic brominated and/or phosphorus containing flame retardant, such as ammonium polyphosphate or decabromodiphenyl oxide wherein the amount of organic or inorganic flame retardant required to achieve an acceptable level of flame retardancy is significantly reduced compared to that needed when the hindered amine is not present.

Abstract: Polyolefins, especially polypropylene, can be made flame retardant by the incorporation therein of a synergistic mixture of a selected hindered amine substituted by an alkoxy, cycloalkoxy or hydroxyalkoxy moiety and a selected organic or inorganic brominated and/or phosphorus containing flame retardant, such as ammonium polyphosphate or decabromodiphenyl oxide wherein the amount of organic or inorganic flame retardant required to achieve an acceptable level of flame retardancy is significantly reduced compared to that needed when the hindered amine is not present.

Abstract: Hindered amine compounds containing a group of the formula where G1 and G2 are independently alkyl of 1 to 4 carbon atoms or are together pentamethylene, Z1 and Z2 are each methyl, or Z1 and Z2 together form a linking moiety which may additionally be substituted by an ester, ether, amide, amino, carboxy or urethane group, and E is alkoxy, cycloalkoxy, aralkoxy, aryloxy, —O—CO—OZ3, —O—Si(Z4)3, —O—PO(OZ5)2 or —O—CH2—OZ6 where Z3, Z4, Z5 and Z6 are selected from the group consisting of hydrogen, an aliphatic, araliphatic and aromatic moiety, when added to a wide variety of polymeric substrates, particularly polyolefins and styrenic polymers, surprisingly bestow flame retardant properties to such compositions.

Abstract: Polyolefins, especially polypropylene, can be made flame retardant by the incorporation therein of a synergistic mixture of a selected hindered amine substituted by an alkoxy, cycloalkoxy or hydroxyalkoxy moiety and a selected organic or inorganic brominated and/or phosphorus containing flame retardant, such as ammonium polyphosphate or decabromodiphenyl oxide wherein the amount of organic or inorganic flame retardant required to achieve an acceptable level of flame retardancy is significantly reduced compared to that needed when the hindered amine is not present.

Abstract: Polyolefins, especially polypropylene, can be made flame retardant by the incorporation therein of a synergistic mixture of a selected hindered amine substituted by an alkoxy, cydoalkoxy or hydroxyalkoxy moiety and a selected organic or inorganic brominated and/or phosphorus containing flame retardant, such as ammonium polyphosphate or decabromodiphenyl oxide wherein the amount of organic or inorganic flame retardant required to achieve an acceptable level of flame retardancy is significantly reduced compared to that needed when the hindered amine is not present.

Abstract: Hindered amine compounds containing a group of the formula 1

Abstract: The present invention is an object-oriented apparatus stored in the memory of a computer system for executing a method for synchronizing schemas between a database and an object-oriented repository. The method includes the steps of initializing a variable, object X, which is of type, Type, with the object on which this method was called and obtaining values for each attribute of the object X from the database. Next, for each attribute of the object X, a comparison is made of the value obtained in the preceding step with value of attribute stored in the repository. A determination is next made as to whether or not any differences were found in the preceding step. If no differences were found, then a determination is made as to whether or not there are more attributes in the object X, and if so, repeat all steps except the first one.

Abstract: A mixture of the compounds identified in the title, their pure isomers and alkane-bridged derivatives are particularly effective in stabilizing polymer compositions, particularly polyolefin compositions.