Abstract: Apparatus and methods are described to program memory cells and verify stored values programmed into the cells. A verify operation can be modified to reduce the time spent to verify the state of memory cells. A scan operation operates to determine the state of a memory cell of group of memory cells being part of a verify in programming, e.g., during a programming loop. A scan operation can determine the cell voltage level, e.g., the low voltage (VL). The scan operation can determine if the cell is in a quick pass write state, e.g., the cells with their voltage (Vth) between the VL and VH. The detect operation determines whether the subsequent VL sensing and verification is to be skipped based on the count of memory cells that exceed VL and those in QPW.

Abstract: A sense amplifier for a memory circuit is presented that can reduce sensing times by introduction of a local reference generator. The sense amplifier includes two capacitors that are pre-charged prior to a sensing operation. A first of the capacitors is connected so that it can discharge through a selected memory cell at a rate dependent on the conductivity of the selected memory cell. After a sensing interval in which the first capacitor can discharge through the selected memory cell, the voltage level on the first capacitor is compared with the voltage level on the second capacitor to determine the result of the sensing operation.

Abstract: Disclosed herein are techniques for generating a temperature independent reference current, which may be used during calibration. The temperature independent reference current may be generated based on a current through an on-chip calibration resistor. This alleviates the need for an off chip calibration resistor, which can be costly and cause slow calibration. A voltage at one terminal of the on chip calibration resistor may be modulated to substantially cancel a temperature coefficient of the on chip calibration resistor. This may result in the current passing through the on chip calibration resistor being temperature independent. The temperature independent reference current may be based on a reference voltage and a target calibration resistance.

Abstract: Disclosed herein are techniques for generating a temperature independent reference current, which may be used during calibration. The temperature independent reference current may be generated based on a current through an on-chip calibration resistor. This alleviates the need for an off chip calibration resistor, which can be costly and cause slow calibration. A voltage at one terminal of the on chip calibration resistor may be modulated to substantially cancel a temperature coefficient of the on chip calibration resistor. This may result in the current passing through the on chip calibration resistor being temperature independent. The temperature independent reference current may be based on a reference voltage and a target calibration resistance.

Abstract: Disclosed herein are techniques for generating a temperature independent reference current, which may be used during calibration. The temperature independent reference current may be generated based on a current through an on-chip calibration resistor. This alleviates the need for an off chip calibration resistor, which can be costly and cause slow calibration. A voltage at one terminal of the on chip calibration resistor may be modulated to substantially cancel a temperature coefficient of the on chip calibration resistor. This may result in the current passing through the on chip calibration resistor being temperature independent. The temperature independent reference current may be compared with a calibration current in a ZQ calibration circuit.