Abstract: A buffer memory in a peripheral controller has dedicated page and word location segments for each one of a multiple number of attached peripheral units. Additionally, an auxiliary segment provides memory for the active status of each one of the multiple number of data transfer cycle operations which may be occurring concurrently and which status can be accessed at the optimum time so that each initiated data transfer cycle can be completed in a time-saving fashion. Memory address control means are provided for accessing page segments and word locations therein in order to insert data therein or to remove data therefrom. A special queue segment is available to provide concurrent status information for each I/O command initiated by a host computer.

Abstract: A peripheral controller executes data transfer operations between a host computer and a multiple number of separate peripheral terminal units. A specialized buffer memory control system provides dedicated page-segments for each one of the peripheral terminal units to enable the peripheral controller to concurrently manage a multiple number of data transfer cycles in an optimum fashion in order to increase the through-put of the data transfer operations.