Abstract: Flat no-leads integrated circuit (IC) packages are formed with solder wettable leadframe terminals. Dies are mounted on die attach pads, bonded to adjacent leadframe terminal structures, and encapsulated in a mold compound. A laser grooving process removes mold compound from a leadframe terminal groove extending along a row of leadframe terminal structures. A saw step cut along the leadframe terminal groove extends partially through the leadframe thickness to define a saw step cut groove. Exposed leadframe surfaces, including surfaces exposed by the saw step cut, are plated with a solder-enhancing material. A singulation cut is performed along the saw step cut groove to define leadframe terminals with end surfaces plated with the solder-enhancing material. The laser grooving process may improve the results of the saw step cut, and the saw step cut may remove mold compound not removed by the laser grooving process.

Abstract: Flat no-leads integrated circuit (IC) packages are formed with solder wettable leadframe terminals. Dies are mounted on die attach pads, bonded to adjacent leadframe terminal structures, and encapsulated in a mold compound. A laser grooving process removes mold compound from a leadframe terminal groove extending along a row of leadframe terminal structures. A saw step cut along the leadframe terminal groove extends partially through the leadframe thickness to define a saw step cut groove. Exposed leadframe surfaces, including surfaces exposed by the saw step cut, are plated with a solder-enhancing material. A singulation cut is performed along the saw step cut groove to define leadframe terminals with end surfaces plated with the solder-enhancing material. The laser grooving process may improve the results of the saw step cut, and the saw step cut may remove mold compound not removed by the laser grooving process.

Abstract: Methods are disclosed for forming flat no-leads packages (e.g., QFN packages) with soldering surfaces that are fully coated, e.g., by a tin immersion process, for improved solder connections of the packages to a PCB or other structure. The method includes forming a flat no-leads package structure including a leadframe terminal structure having an exposed top or bottom surface; forming a first coating of a first coating material (e.g., tin) on the exposed top or bottom surface; cutting through a full thickness of the leadframe terminal structure to define an exposed terminal sidewall surface; and forming a second coating of a second coating material (e.g., tin) over the full height of the exposed terminal sidewall surface. The coating (e.g., tin immersion coating) covering the full height of the leadframe terminal sidewall may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.

Abstract: Methods are disclosed for forming flat leads packages (e.g., QFP or SOT packages) having leads coated with a solder-enhancing material for improved solder mounting to a PCB or other structure. The method may include forming a flat leads package structure including an array of encapsulated IC structures formed on a common leadframe. An isolation cutting process may be performed to electrically isolate the IC structures from each other and define a plurality of leadframe leads extending from each IC structure. After the isolation cutting process, an immersion coating process is performed to coat exposed surfaces of the leadframe leads, including the full surface area of a distal end of each leadframe lead. The coating (e.g., tin coating) covering the distal ends of the leadframe leads may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.

Abstract: Methods are disclosed for forming flat leads packages (e.g., QFP or SOT packages) having leads coated with a solder-enhancing material for improved solder mounting to a PCB or other structure. The method may include forming a flat leads package structure including an array of encapsulated IC structures formed on a common leadframe. An isolation cutting process may be performed to electrically isolate the IC structures from each other and define a plurality of leadframe leads extending from each IC structure. After the isolation cutting process, an immersion coating process is performed to coat exposed surfaces of the leadframe leads, including the full surface area of a distal end of each leadframe lead. The coating (e.g., tin coating) covering the distal ends of the leadframe leads may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.

Abstract: Methods are disclosed for forming flat no-leads packages (e.g., QFN packages) with soldering surfaces that are fully coated, e.g., by a tin immersion process, for improved solder connections of the packages to a PCB or other structure. The method includes forming a flat no-leads package structure including a leadframe terminal structure having an exposed top or bottom surface; forming a first coating of a first coating material (e.g., tin) on the exposed top or bottom surface; cutting through a full thickness of the leadframe terminal structure to define an exposed terminal sidewall surface; and forming a second coating of a second coating material (e.g., tin) over the full height of the exposed terminal sidewall surface. The coating (e.g., tin immersion coating) covering the full height of the leadframe terminal sidewall may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.

Abstract: An apparatus includes a lead frame paddle configured for mounting a semiconductor die. The apparatus further includes a plating area formed on the lead frame paddle. The plating area is configured to receive a down bond from a semiconductor die placed on the lead frame paddle. The apparatus further includes an exposed gap between an outer edge of the plating area and an outer edge of the lead frame paddle.

Abstract: An integrated circuit device having improved delamination properties is provided. The integrated circuit may include a leadframe having a die support area supporting an integrated circuit die, and a plurality of leadframe leads. Surfaces of the leadframe leads are roughened by a roughening process to form roughened surfaces having an average roughness Ra. A thin plating layer is formed over the roughened leadframe lead surfaces, with a plating layer thickness of less than 40 times the roughness Ra of the leadframe lead surfaces, such that the thin plating layer is received into the roughened leadframe lead surface contours and thereby itself has a contoured outer surface. A molding material applied to the structure may directly contact and adhere to the contoured surface of the thin plating layer. The adhesion between the molding material and the contoured plating layer may reduce or eliminate delamination of the molding material from the leadframe.

Abstract: According to an embodiment of the present disclosure, a method for manufacturing an integrated circuit (IC) device may include mounting an IC chip onto a center support structure of a leadframe. The leadframe may include: a plurality of pins extending from the center support structure; a groove running perpendicular to the individual pins of the plurality of pins around the center support structure; and a bar connecting the plurality of pins remote from the center support structure.

Abstract: According to an embodiment of the present disclosure, a leadframe for an integrated circuit (IC) device may comprise a center support structure for mounting an IC chip, a plurality of pins extending from the center support structure, and a bar connecting the plurality of pins remote from the center support structure. Each pin of the plurality of pins may include a dimple.

Abstract: According to an embodiment of the present disclosure, a leadframe for an integrated circuit (IC) device may comprise a center support structure for mounting an IC chip, a plurality of pins extending from the center support structure, and a bar connecting the plurality of pins remote from the center support structure. Each pin of the plurality of pins may include a dimple.

Abstract: According to an embodiment of the present disclosure, a method for manufacturing an integrated circuit (IC) device may include mounting an IC chip onto a center support structure of a leadframe, bonding the IC chip to at least some of the plurality of pins, encapsulating the leadframe and bonded IC chip, sawing a step cut into the encapsulated leadframe, plating the exposed portion of the plurality of pins, and cutting the IC package free from the bar. The leadframe may include a plurality of pins extending from the center support structure and a bar connecting the plurality of pins remote from the center support structure. The step cut may be sawn into the encapsulated leadframe along a set of cutting lines using a first saw width without separating the bonded IC package from the bar, thereby exposing at least a portion of the plurality of pins.

Abstract: A reduced width tie bar and a common lead hold a die paddle of each integrated circuit SOT-23 package to a leadframe within a strip of leadframes after isolating signal leads from the leadframe. Strip testing of most devices in the SOT-23 lead packages may then be performed. The common lead may be at the center of an edge of the SOT-23 package. Also the common lead may be any one of the leads of the SOT-23 package. The reduced width tie bar may be downstream of the epoxy encapsulation flow for better package integrity.