Patents by Inventor Rani R. Narayan

Rani R. Narayan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit selective scaling
    Patent number: 7882463
    Abstract: The invention includes a solution for selectively scaling an integrated circuit (IC) design by: layer, region or cell, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: February 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Fook-Luen Heng, Jason D. Hibbeler, Kevin W. McCullen, Rani R. Narayan, Stephen L. Runyon, Robert F. Walker
  • Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs
    Patent number: 7484197
    Abstract: A method comprises extracting a hierarchical grid constraint set and modeling one or more critical objects of at least one cell as a variable set. The method further comprises solving a linear programming problem based on the hierarchical grid constraint set with the variable set to provide initial locations of the critical objects of the at least one cell and determining target on-grid locations of the one or more critical objects in the at least one cell using the results of the linear programming solution.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: January 27, 2009
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Allen, Michael S. Gray, Fook-Luen Heng, Jason D. Hibbeler, Kevin W. McCullen, Rani R. Narayan, Robert F. Walker, Xin Yuan
  • INTEGRATED CIRCUIT SELECTIVE SCALING
    Publication number: 20080148210
    Abstract: The invention includes a solution for selectively scaling an integrated circuit (IC) design by: layer, region or cell, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield.
    Type: Application
    Filed: February 22, 2008
    Publication date: June 19, 2008
    Inventors: Fook-Luen Heng, Jason D. Hibbeler, Kevin W. McCullen, Rani R. Narayan, Stephen L. Runyon, Robert F. Walker
  • Integrated circuit selective scaling
    Patent number: 7363601
    Abstract: Methods, systems and program products are disclosed for selectively scaling an integrated circuit (IC) design: by layer, by unit, or by ground rule, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield where new technologies such as maskless fabrication are implemented.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: April 22, 2008
    Assignee: International Business Machines Corporation
    Inventors: Fook-Luen Heng, Jason D. Hibbeler, Kevin W. McCullen, Rani R. Narayan, Stephen L. Runyon, Robert F. Walker