Abstract: A circuit includes a first power transistor including a first control input and first and second current terminals. The circuit includes a second power transistor including a second control input and third and fourth current terminals. Third current terminal couples to the first current terminal, and the fourth current terminal couples to the second current terminal at an output node. An error amplifier generates an error signal based on a difference between a reference voltage and an output voltage on the output node. An adaptive buffer couples to an output of the error amplifier and couples to the first and second control inputs. The adaptive buffer causes the first power transistor to be on through a range of output current and to cause the second power transistor to be on through some, but not all, of the range of output current.

Abstract: Methods and apparatus for detecting a zero inductor current to control switch transitions for a power converter. An example method includes outputting a first voltage and a first current, receiving the first voltage and output a second voltage into an input of a comparator, when the second voltage is above a third voltage, outputting a first output voltage, when the second voltage is below the third voltage, outputting a second output voltage, determining when the first current is zero based the output of the comparator, enabling a set of switches based on when the first current is zero.

Abstract: Methods and apparatus for detecting a zero inductor current to control switch transitions for a power converter. An example method includes outputting a first voltage and a first current, receiving the first voltage and output a second voltage into an input of a comparator, when the second voltage is above a third voltage, outputting a first output voltage, when the second voltage is below the third voltage, outputting a second output voltage, determining when the first current is zero based the output of the comparator, enabling a set of switches based on when the first current is zero.

Abstract: Methods and apparatus for detecting a zero inductor current to control switch transitions for a power converter. An example method includes outputting a first voltage and a first current, receiving the first voltage and output a second voltage into an input of a comparator, when the second voltage is above a third voltage, outputting a first output voltage, when the second voltage is below the third voltage, outputting a second output voltage, determining when the first current is zero based the output of the comparator, enabling a set of switches based on when the first current is zero.

Abstract: Single-input-multiple-output (SIMO) DC-DC converters and SIMO DC-DC converter control circuits are disclosed. An example DC-DC converter control circuit includes a switch controller to control respective switches of a SIMO DC-DC voltage converter that has multiple output circuits. The example control circuit also includes an arbitration circuit that determines a first one of the output circuits to have priority over other ones of the output circuits based on a priority signal, and selects a first output circuit to be charged during a first time slot based on the priority signal and based on first kick signals indicating that the at least two output circuits are to be charged. The control circuit also includes a next kick detector that determines a second one of the output circuits to be charged during a second time slot after the first time slot based on the priority.

Abstract: Methods and apparatus for detecting a zero inductor current to control switch transitions for a power converter. An example method includes outputting a first voltage and a first current, receiving the first voltage and output a second voltage into an input of a comparator, when the second voltage is above a third voltage, outputting a first output voltage, when the second voltage is below the third voltage, outputting a second output voltage, determining when the first current is zero based the output of the comparator, enabling a set of switches based on when the first current is zero.

Abstract: A circuit includes circuit portions operating from separate power supplies which are switched sequentially. An output of a first portion powered by a power supply (A) is provided as an input to a second portion powered by another power supply (B). Power supply (A) is switched-ON a delay interval later than power supply (B). In an embodiment, the first portion also receives a control input which enables or disables response of the first portion to changes in its inputs. An active circuit is connected between the control terminal and a constant reference potential node of the circuit, and has one transistor of a current-mirror pair connected across supplies (A) and (B). The active circuit connects the control terminal to the constant reference potential node in the delay interval, but is an open circuit otherwise. Power dissipation in the circuit is thereby reduced.

Abstract: An apparatus and method for reducing interference signals using multiphase clocks. An integrated circuit includes a digital circuit and an analog circuit. The digital circuit includes a derived clock circuit configured to receive a root clock having a frequency D*f, D being a divide factor, to divide the root clock by D, and generate multiphase clocks having N phases. N circuits of the digital circuit are configured to receive a corresponding one of the N phases, with edges of the multiphase clocks being spread over the N phases. The multiphase clocks cause a frequency shift in interference signals generated by reduced periodic peak currents drawn by the N circuits from f to N*f and harmonics thereof. The analog circuit receives an in-band range of signals. A value of N is configured to shift the interference signals outside the in-band range of signals.

Abstract: The systems and methods of auto-configurable switching/linear regulation disclosed herein enable a device to operate in both DC-to-DC switching regulation and linear regulation applications. The systems and methods disclosed herein differentiate between switching and linear mode. If the application is for a linear regulator, there will only be a capacitor on the output. If the application is for switching mode regulation, there will be an inductor and a capacitor on the output. Then based on the determination, the mode is selected and the hardware is converted into switching regulator operation or linear regulator operation.

Abstract: The systems and methods of auto-configurable switching/linear regulation disclosed herein enable a device to operate in both DC-to-DC switching regulation and linear regulation applications. The systems and methods disclosed herein differentiate between switching and linear mode. If the application is for a linear regulator, there will only be a capacitor on the output. If the application is for switching mode regulation, there will be an inductor and a capacitor on the output. Then based on the determination, the mode is selected and the hardware is converted into switching regulator operation or linear regulator operation.

Abstract: A circuit includes circuit portions operating from separate power supplies which are switched sequentially. An output of a first portion powered by a power supply (A) is provided as an input to a second portion powered by another power supply (B). Power supply (A) is switched-ON a delay interval later than power supply (B). In an embodiment, the first portion also receives a control input which enables or disables response of the first portion to changes in its inputs. An active circuit is connected between the control terminal and a constant reference potential node of the circuit, and has one transistor of a current-mirror pair connected across supplies (A) and (B). The active circuit connects the control terminal to the constant reference potential node in the delay interval, but is an open circuit otherwise. Power dissipation in the circuit is thereby reduced.

Abstract: A circuit includes circuit portions operating from separate power supplies which are switched sequentially. An output of a first portion powered by a power supply (A) is provided as an input to a second portion powered by another power supply (B). Power supply (A) is switched-ON a delay interval later than power supply (B). In an embodiment, the first portion also receives a control input which enables or disables response of the first portion to changes in its inputs. An active circuit is connected between the control terminal and a constant reference potential node of the circuit, and has one transistor of a current-mirror pair connected across supplies (A) and (B). The active circuit connects the control terminal to the constant reference potential node in the delay interval, but is an open circuit otherwise. Power dissipation in the circuit is thereby reduced.

Abstract: A circuit includes circuit portions operating from separate power supplies which are switched sequentially. An output of a first portion powered by a power supply (A) is provided as an input to a second portion powered by another power supply (B). Power supply (A) is switched-ON a delay interval later than power supply (B). In an embodiment, the first portion also receives a control input which enables or disables response of the first portion to changes in its inputs. An active circuit is connected between the control terminal and a constant reference potential node of the circuit, and has one transistor of a current-mirror pair connected across supplies (A) and (B). The active circuit connects the control terminal to the constant reference potential node in the delay interval, but is an open circuit otherwise. Power dissipation in the circuit is thereby reduced.

Abstract: A power management (PM) system architecture for a controlled SoC detects availability of power supply for signal-driving at a given node inside a chip, and uses a timer, a discharge mechanism with trigger for starting/stopping a discharge process, and a comparator for monitoring a measured voltage of an intended node during the discharge process. Enabling the discharge mechanism for a known time period helps detection. Power supply can be internally generated in the chip or from a source on board. The architecture detects if the node is driven or floating, an undriven floating node causing a dip in the measured voltage. The measured voltage does not have a dip when the node is driven. The architecture is also configured so that when there is a required on-board external power supply, an internal power supply is disabled to avoid a race-condition. The architecture obviates a dedicated IO pin for mode-indication.

Abstract: A device for testing low dropout (LDO) regulator is disclosed. In one embodiment, a device for testing LDO regulators includes an absolute value measurement module for measuring absolute output voltages of the LDO regulators including a resistor scaling array for generating candidate voltages based on a first output voltage of the LDO regulators, a multiplexer for forwarding one of the candidate voltages selected by a binary search algorithm, and a comparator for generating a first test output by comparing the candidate voltage with an external reference voltage, and a DC load regulation measurement module for measuring corresponding DC regulation voltages of the LDO regulators including a switch for applying an internal test load to a second output voltage of the LDO regulators, and the comparator for generating a second test output by comparing a reference voltage with the second output voltage modified by the internal test load.

Abstract: An apparatus and method for reducing interference signals using multiphase clocks. An integrated circuit includes a digital circuit and an analog circuit. The digital circuit includes a derived clock circuit configured to receive a root clock having a frequency D*f, D being a divide factor, to divide the root clock by D, and generate multiphase clocks having N phases. N circuits of the digital circuit are configured to receive a corresponding one of the N phases, with edges of the multiphase clocks being spread over the N phases. The multiphase clocks cause a frequency shift in interference signals generated by reduced periodic peak currents drawn by the N circuits from f to N*f and harmonics thereof. The analog circuit receives an in-band range of signals. A value of N is configured to shift the interference signals outside the in-band range of signals.

Abstract: A low power bandgap reference circuit for retention mode in system on chips (SoCs). A switched bandgap reference includes bandgap reference circuit coupled to a storage capacitor through a switch. A logic having a set of control signals controls the switch and the bandgap reference circuit such that during a retention mode the bandgap reference circuit and the switch are active for a first time interval in response to the set of control signals to recharge the storage capacitor and then inactive for a second time interval in response to the set of control signals that decouples the bandgap reference circuit from the storage capacitor. The charge stored in the storage capacitor is used to generate a reference voltage.

Abstract: A power management (PM) system architecture for a controlled SoC detects availability of power supply for signal-driving at a given node inside a chip, and uses a timer, a discharge mechanism with trigger for starting/stopping a discharge process, and a comparator for monitoring a measured voltage of an intended node during the discharge process. Enabling the discharge mechanism for a known time period helps detection. Power supply can be internally generated in the chip or from a source on board. The architecture detects if the node is driven or floating, an undriven floating node causing a dip in the measured voltage. The measured voltage does not have a dip when the node is driven. The architecture is also configured so that when there is a required on-board external power supply, an internal power supply is disabled to avoid a race-condition. The architecture obviates a dedicated IO pin for mode-indication.

Abstract: A device for testing low dropout (LDO) regulator is disclosed. In one embodiment, a device for testing LDO regulators includes an absolute value measurement module for measuring absolute output voltages of the LDO regulators including a resistor scaling array for generating candidate voltages based on a first output voltage of the LDO regulators, a multiplexer for forwarding one of the candidate voltages selected by a binary search algorithm, and a comparator for generating a first test output by comparing the candidate voltage with an external reference voltage, and a DC load regulation measurement module for measuring corresponding DC regulation voltages of the LDO regulators including a switch for applying an internal test load to a second output voltage of the LDO regulators, and the comparator for generating a second test output by comparing a reference voltage with the second output voltage modified by the internal test load.

Abstract: A constant current source for generating a constant reference current that is relatively temperature insensitive. The constant current source comprises: i) first circuitry for generating a first output current that increases with increases in temperature; ii) second circuitry for generating a second output current that decreases with increases in temperature; and iii) a current combiner circuit that combines the first and second output currents to thereby generate the constant reference current. A change in the first output current caused by a temperature change is at least partially offset by a change in the second output current caused by the temperature change.