Patents by Inventor Ranjith SIDDALINGA

Ranjith SIDDALINGA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System for testing and verification of serial communication protocols
    Patent number: 12177029
    Abstract: A system is provided including an adaptive scoreboard for testing and verification of serial communication protocols. The scoreboard is configured to: receive, through a first port, actual data packets from a design under test (DUT), and, through a first pattern detection engine, based on a set of pre-defined skip patterns, identify a first set of redundant data packets from the actual data packets; receive, through a second port, reference data packets from a reference model, and, through a second pattern detection engine, based on the set of pre-defined skip patterns, identify a second set of redundant data packets from the reference data packets; and compare the actual data packets and reference data packets to verify the functionality of the DUT by at least one of ignoring the first and second sets of redundant data packets and comparing the first and second sets of redundant data packets if they are matching.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: December 24, 2024
    Assignee: SILICONCH SYSTEMS PVT LTD
    Inventors: Sirisha Munnangi, Kaustubh Kumar, Ranjith Siddalinga
  • SYSTEM FOR TESTING AND VERIFICATION OF SERIAL COMMUNICATION PROTOCOLS
    Publication number: 20240421946
    Abstract: A system is provided including an adaptive scoreboard for testing and verification of serial communication protocols. The scoreboard is configured to: receive, through a first port, actual data packets from a design under test (DUT), and, through a first pattern detection engine, based on a set of pre-defined skip patterns, identify a first set of redundant data packets from the actual data packets; receive, through a second port, reference data packets from a reference model, and, through a second pattern detection engine, based on the set of pre-defined skip patterns, identify a second set of redundant data packets from the reference data packets; and compare the actual data packets and reference data packets to verify the functionality of the DUT by at least one of ignoring the first and second sets of redundant data packets and comparing the first and second sets of redundant data packets if they are matching.
    Type: Application
    Filed: November 17, 2023
    Publication date: December 19, 2024
    Inventors: Sirisha MUNNANGI, Kaustubh KUMAR, Ranjith SIDDALINGA