Abstract: A data link layer device and a packet encapsulation method are provided. The data link layer device includes a first and a second first-in-first-out (FIFO) module. The first FIFO module receives and stores multiple first data from an upper-layer module, and removes data gaps from the first data to store the first data in a continuous form. When the first FIFO module is not empty, the first FIFO module generates data of different lengths based on the current amount of data stored temporarily in the first FIFO module and a preset data length. When the data queue of the second FIFO module has enough space to receive the first data, the first FIFO module transfers the first data to the second FIFO module, and the first FIFO module transfers a header including the data length to a header queue of the second FIFO module.

Abstract: A data link layer device and a packet encapsulation method are provided. The data link layer device includes a first and a second first-in-first-out (FIFO) module. The first FIFO module receives and stores multiple first data from an upper-layer module, and removes data gaps from the first data to store the first data in a continuous form. When the first FIFO module is not empty, the first FIFO module generates data of different lengths based on the current amount of data stored temporarily in the first FIFO module and a preset data length. When the data queue of the second FIFO module has enough space to receive the first data, the first FIFO module transfers the first data to the second FIFO module, and the first FIFO module transfers a header including the data length to a header queue of the second FIFO module.

Abstract: A ring bus and a credit allocation method are provided. The ring bus includes a slave module and multiple master modules. The slave module includes an injection table and a state table, and is configured to generate a credit signal including a node identity and an active code. The master modules are coupled to the slave module to form a ring path. The slave module determines whether the credit signal is a newly injected credit signal, and determines the node identity of the credit signal according to the injection table or the state table. The slave module transmits the credit signal to the master module corresponding to the node identity through the ring path according to the node identity. The slave module uses a corresponding idle entry to receive a credit request signal provided by the master device consuming a credit of the credit signal.

Abstract: A ring bus and a credit allocation method are provided. The ring bus includes a slave module and multiple master modules. The slave module includes an injection table and a state table, and is configured to generate a credit signal including a node identity and an active code. The master modules are coupled to the slave module to form a ring path. The slave module determines whether the credit signal is a newly injected credit signal, and determines the node identity of the credit signal according to the injection table or the state table. The slave module transmits the credit signal to the master module corresponding to the node identity through the ring path according to the node identity. The slave module uses a corresponding idle entry to receive a credit request signal provided by the master device consuming a credit of the credit signal.

Abstract: A memory integrated circuit and a pre-fetch method thereof are provided. The memory integrated circuit includes an interface circuit, a memory, a memory controller, and a pre-fetch accelerator circuit. The interface circuit receives a normal read request from an external device. After the pre-fetch accelerator circuit sends a pre-fetch request to the memory controller, the pre-fetch accelerator circuit pre-fetches at least one pre-fetch data from the memory through the memory controller. When the pre-fetch data in the pre-fetch accelerator circuit has a target data of the normal read request, the pre-fetch accelerator circuit takes the target data from the pre-fetch data and returns the target data to the interface circuit. When the pre-fetch data in the pre-fetch accelerator circuit has no target data, the pre-fetch accelerator circuit sends the normal read request with higher priority than the pre-fetch request to the memory controller.

Abstract: A memory integrated circuit and a pre-fetch address determining method thereof are provided. The memory integrated circuit includes an interface circuit, a memory, a memory controller, and a pre-fetch accelerator circuit. The interface circuit receives a normal read request from an external device. When the pre-fetch accelerator circuit receives the normal read request from the interface circuit, the pre-fetch accelerator circuit adds a current address of the normal read request to a training address group as a new training address. The pre-fetch accelerator circuit reorders a plurality of training addresses of the training address group. The pre-fetch accelerator circuit calculates a pre-fetch stride according to the reordered training addresses of the training address group. The pre-fetch accelerator circuit calculates a pre-fetch address of a pre-fetch request according to the pre-fetch stride and the current address.