Abstract: An improved method for etching a magnetic tunneling junction (MTJ) structure is achieved. A stack of MTJ layers is provided on a bottom electrode. The MTJ stack is patterned to form a MTJ device wherein sidewall damage or sidewall redeposition is formed on sidewalls of the MTJ device. A dielectric layer is deposited on the MTJ device and the bottom electrode. The dielectric layer is etched away using ion beam etching at an angle relative to vertical of greater than 50 degrees wherein the dielectric layer on the sidewalls is etched away and wherein sidewall damage or sidewall redeposition is also removed and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.

Abstract: An improved method for etching a magnetic tunneling junction (MTJ) structure is achieved. A stack of MTJ layers is provided on a bottom electrode. The MTJ stack is patterned to form a MTJ device wherein sidewall damage or sidewall redeposition is formed on sidewalls of the MTJ device. A dielectric layer is deposited on the MTJ device and the bottom electrode. The dielectric layer is etched away using ion beam etching at an angle relative to vertical of greater than 50 degrees wherein the dielectric layer on the sidewalls is etched away and wherein sidewall damage or sidewall redeposition is also removed and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.

Abstract: A tennis practice device that has a rebound surface made out of composite material consisting of cement, ground calcium silica, cellulose fibers, wood fibers and other select additives such as fly ash and a sound dampening material sandwiched between the rebound surface and the support structure.

Abstract: A method for in-situ monitoring a process in a plasma processing system having a plasma processing chamber is disclosed. The method includes positioning a substrate in the plasma processing chamber. The method also includes striking a plasma within the plasma processing chamber while the substrate is disposed within the plasma processing chamber. The method further includes obtaining a measured self-bias voltage that exists after the plasma is struck, the measured self-bias voltage value having a first value when the plasma is absent and at least a second value different from the first value when the plasma is present. The method also includes correlating the measured self-bias voltage value with an attribute of the process, if the measured self-bias voltage value is outside of a predefined self-bias voltage value envelope.

Abstract: A method of stripping an integrated circuit (IC) structure having a photoresist material and an organosilicate glass (OSG) material is described. The method comprises feeding a nitrous oxide (N2O) gas into a reactor, generating a plasma in the reactor and stripping the photoresist. The stripping process provides a high selectivity between the photoresist and the OSG material.

Abstract: A method of etching a barrier layer in an integrated circuit (IC) wherein said barrier layer is composed of silicon nitride or silicon carbide. The method comprises receiving an etched IC structure having an exposed barrier layer. The method then proceeds to apply an etchant gas mixture comprising a nitrous oxide (N2O) gas and a fluoromethane (CH3F) gas. The etchant gas mixture provides a relatively high selectivity between the barrier layer to an adjacent dielectric layer.

Abstract: A method of forming a feature in a porous low-K dielectric layer is provided. A porous low-K dielectric layer is placed over a substrate. A patterned photoresist mask is placed over the porous low-K dielectric layer. A feature is etched into the porous low-K dielectric layer. A protective layer is deposited over the feature after the etching the feature. The patterned photoresist mask is stripped, so that part of the protective layer is removed, where protective walls formed from the protective layer remain in the feature.

Abstract: A method of forming a feature in a porous low-K dielectric layer is provided. A porous low-K dielectric layer is placed over a substrate. A patterned photoresist mask is placed over the porous low-K dielectric layer. A feature is etched into the porous low-K dielectric layer. A protective layer is deposited over the feature after the etching the feature. The patterned photoresist mask is stripped, so that part of the protective layer is removed, where protective walls formed from the protective layer remain in the feature.

Abstract: A method for in-situ monitoring a process in a plasma processing system having a plasma processing chamber is disclosed. The method includes positioning a substrate in the plasma processing chamber. The method also includes striking a plasma within the plasma processing chamber while the substrate is disposed within the plasma processing chamber. The method further includes obtaining a measured self-bias voltage that exists after the plasma is struck, the measured self-bias voltage value having a first value when the plasma is absent and at least a second value different from the first value when the plasma is present. The method also includes correlating the measured self-bias voltage value with an attribute of the process, if the measured self-bias voltage value is outside of a predefined self-bias voltage value envelope.

Abstract: A method for in-situ monitoring a process in a plasma processing system having a plasma processing chamber is disclosed. The method includes positioning a substrate in the plasma processing chamber. The method also includes striking a plasma within the plasma processing chamber while the substrate is disposed within the plasma processing chamber. The method further includes obtaining a measured impedance that exists after the plasma is struck, the measured impedance value having a first value when the plasma is absent and at least a second value different from the first value when the plasma is present. The method also includes correlating the measured impedance value with an attribute of the process, if the measured impedance value is outside of a predefined impedance value envelope.

Abstract: A method for in-situ monitoring a process in a plasma processing system having a plasma processing chamber is disclosed. The method includes positioning a substrate in the plasma processing chamber. The method also includes striking a plasma within the plasma processing chamber while the substrate is disposed within the plasma processing chamber. The method further includes obtaining a measured plasma frequency that exists after the plasma is struck, the measured plasma frequency value having a first value when the plasma is absent and at least a second value different from the first value when the plasma is present. The method also includes correlating the measured plasma frequency value with an attribute of the process, if the measured plasma frequency value is outside of a predefined plasma frequency value envelope.

Abstract: A method for generating an organic plug within a via is described. The via resides in an integrated circuit (IC) structure having a silicon containing dielectric material. The method for generating the organic plug includes applying an organic compound such as a bottom antireflective coating. The organic compound occupies the via. The method then proceeds to feed a nitrous oxide (N2O) gas into a reactor and generates a plasma in the reactor. A significant portion of the organic compound is removed leaving behind an organic plug to occupy the via. The organic plug is typically generated during dual damascene processing.

Abstract: A method of forming a feature in a porous low-K dielectric layer is provided. A porous low-K dielectric layer is placed over a substrate. A patterned photoresist mask is placed over the porous low-K dielectric layer. A feature is etched into the porous low-K dielectric layer. A protective layer is deposited over the feature after the etching the feature. The patterned photoresist mask is stripped, so that part of the protective layer is removed, where protective walls formed from the protective layer remain in the feature.

Abstract: A method of removing a photoresist layer from an integrated circuit (IC) structure having an etched dielectric material with an exposed barrier layer that covers a copper interconnect. The barrier layer is composed of a material such as silicon nitride or silicon carbide. The method includes feeding a gas mixture that compromises carbon monoxide (CO) into a reactor. A plasma is then generated within the reactor. The photoresist layer is then selectively removed with little or no etching of the exposed barrier layer.

Abstract: A method for generating an organic plug within a via is described. The via resides in an integrated circuit (IC) structure having a silicon containing dielectric material. The method for generating the organic plug includes applying an organic compound such as a bottom antireflective coating. The organic compound occupies the via. The method then proceeds to feed a nitrous oxide (N2O) gas into a reactor and generates a plasma in the reactor. A significant portion of the organic compound is removed leaving behind an organic plug to occupy the via. The organic plug is typically generated during dual damascene processing.

Abstract: A method of etching a barrier layer in an integrated circuit (IC) wherein said barrier layer is composed of silicon nitride or silicon carbide. The method comprises receiving an etched IC structure having an exposed barrier layer. The method then proceeds to apply an etchant gas mixture comprising a nitrous oxide (N2O) gas and a fluoromethane (CH3F) gas. The etchant gas mixture provides a relatively high selectivity between the barrier layer to an adjacent dielectric layer.

Abstract: A method of stripping an integrated circuit (IC) structure having a photoresist material and an organosilicate glass (OSG) material is described. The method comprises feeding a nitrous oxide (N2O) gas into a reactor, generating a plasma in the reactor and stripping the photoresist. The stripping process provides a high selectivity between the photoresist and the OSG material.

Abstract: A method for removing organic material over a substrate is provided. The substrate is placed in a plasma processing chamber. A first gas is provided to an inner zone within the plasma processing chamber. A second gas is provided to an outer zone of the plasma processing chamber, wherein the outer zone surrounds the inner zone and the second gas has a carbon containing component, wherein a concentration of the carbon containing component of the second gas is greater than a concentration of the carbon containing component in the first gas. Plasmas are simultaneously generated from the first gas and second gas. Some or all of the organic material is removed using the generated plasmas.

Abstract: Process for etching features in wafers incorporating OSG dielectrics. The process results at once in minimal RIE lag, minimal bowing of the features formed by the etch process, good etch profiles, good resist selectivity, and good etch uniformity across the wafer. In order to provide these desirable results, a novel etch gas mixture, including CH2F2 and CF4 is employed. According to one embodiment of the present invention, this novel gas mixture is employed as part of a three-step etch process wherein the several etch steps have varying degrees of etch selectivity between wafer components. The methodology of the present invention is capable of implementation on a wide variety of existing semiconductor etch equipment.

Abstract: A method of etching a stack using a fluorine containing gas and an ammonia containing gas is provided. Generally, the stack is placed in a plasma processing chamber. A fluorine containing gas is flowed into the plasma processing chamber. An ammonia containing gas is flowed into the plasma processing chamber. A plasma is generated. The stack is then etched.