Abstract: Disclosed are embodiments of a method that provides for pre-production run development of a fail signature database, which stores fail signatures for systematic defects and corresponding root causes. The fail signatures in the database is subsequently accessed and used for a variety of purposes. For example, the fail signatures are evaluated and, based on the results of the evaluation, actions are taken to prevent specific systematic defects from occurring during production runs and/or to allow for early detection of specific systematic defects during production runs. In some embodiments, following production runs, new fail signatures from failing production chips are developed and compared against the fail signatures in the fail signature database. In some embodiments, when a signature match indicates that a particular production chip has a same systematic defect with a same root cause as a particular prototype chip in-line advanced process control (APC) is performed.

Abstract: Disclosed are embodiments of a method that provides for pre-production run development of a fail signature database, which stores fail signatures for systematic defects and corresponding root causes. The fail signatures in the database is subsequently accessed and used for a variety of purposes. For example, the fail signatures are evaluated and, based on the results of the evaluation, actions are taken to prevent specific systematic defects from occurring during production runs and/or to allow for early detection of specific systematic defects during production runs. In some embodiments, following production runs, new fail signatures from failing production chips are developed and compared against the fail signatures in the fail signature database. In some embodiments, when a signature match indicates that a particular production chip has a same systematic defect with a same root cause as a particular prototype chip in-line advanced process control (APC) is performed.

Abstract: A method and apparatus are disclosed in which defect behavior in an integrated circuit is discovered and modeled rather than assuming defect behavior in the form of a fault. A plurality of tests are performed on an integrated circuit to produce passing and failing responses. The failing responses are examined in conjunction with circuit description data to identify fault locations. For at least certain of the fault locations, the logic-level conditions at neighboring locations which describe the behavior of a failing response are identified. Those logic level conditions are combined into a macrofault for that location. The macrofault is then validated and can be then used to identify more tests for further refining the diagnosis. Because of the rules governing abstracts, this abstract should not be used to construe the claims.