Abstract: A three-transistor SRAM memory cell includes a bistable field-effect transistor having a fully depleted floating channel region and a hysteretic gate voltage characteristic curve. The bistable field-effect transistor has a gate to be connected to a first bit line for the purpose of writing to the memory cell and a second channel terminal to be connected to a second bit line for the purpose of reading from the memory cell. The two bit lines can be identical. The connection between the bit lines and the bistable transistor can be effected through first and second respective transistors which are each controlled by a respective word line.