Abstract: Aspects of the present disclosure generally relate to a microelectronic package including a plurality of through vias having walls in a glass interposer having a top portion and a bottom portion. The microelectric package may also include a stress relief barrier on at least a portion of the top and bottom portions of the glass interposer. The microelectric package may further include a metallization seed layer on at least a portion of the stress relief layer and a conductor on at least a portion of the metallization seed layer. The conductor extends through at least a portion of the plurality of the through vias, forming a plurality of metalized through package vias. At least a portion of the through vias are filled with the stress relief layer or the metallization seed layer.

Abstract: The various embodiments of the present invention provide fine pitch, chip-to-substrate hybrid interconnect assemblies, as well as methods of making and using the assemblies. The hybrid assemblies generally include a semiconductor having a die pad disposed thereon, a substrate having a substrate pad disposed thereon, and a polymer layer disposed between the surface of the die pad and the surface of the substrate pad. In addition, at least a portion of the surface of the die pad is metallically bonded to at least a portion of the surface of the substrate pad and at least a portion of the surface of the die pad is chemically bonded to at least a portion of the surface of the substrate pad.

Abstract: Disclosed are any electronic system or module which includes embedded actives and discrete passives, and methods for use in fabricating packages containing embedded active devices and/or discrete passive devices. Exemplary apparatus comprises a plurality of build-up layers defining circuit interconnections and that comprise one or more thin film type of embedded passive devices, at least a cavity formed in the build-up layers, and at least an active device and/or at least a discrete passive device disposed in the cavity and electrically connected to the circuit interconnections of the build-up layers. A stiffener may be coupled to an exposed (back) surface of the active device and to an adjacent surface of the build-up layers. The build-up layers may be mounted to a core, and the core may be attached to a printed circuit board. Alternatively, a bottom surface of the build-up layers may be mounted to a printed circuit board without core.

Abstract: The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.

Abstract: Disclosed are three-dimensional dielectric structures on high surface area electrodes and fabrication methods. Exemplary structures comprise a copper foil substrate, trench electrodes or high surface area porous electrode structures formed on the substrate, a insulating thin film formed on the surface and laminating the foil on a organic substrate. A variety of materials may be used to make the films including perovksite ceramics such as barium titanate, strontium titanate, barium strontium titanate (BST), lead zirconate titanate (PZT); other intermediate dielectric constant films such as zinc oxide, aluminum nitride, silicon nitride; typical paraelectrics such as tantalum oxide, alumina, and titania. The films may be fabricated using sol-gel, hydrothermal synthesis, anodization or vapor deposition techniques.

Abstract: The present invention describes systems and methods for providing high-density capacitors. An exemplary embodiment of the present invention provides a high-density capacitor system comprising a substrate and a porous conductive layer formed on the substrate, wherein the porous conductive layer is formed in accordance with a predetermined pattern. Furthermore, the high-density capacitor system includes a dielectric material formed on the porous conductive layer and a second conductive layer formed on the dielectric material. Additionally, the high-density capacitor system includes a plurality of conductive pads configured in communication with the second conductive layer.

Abstract: Disclosed are ferroelectric and ferromagnetic noise isolation structures that reduce electromagnetic interference and noise in integrated circuit devices and system architectures. Representative structures comprise two or more devices that are vertically disposed relative to one another, and a thin ferroelectric or ferromagnetic film layer disposed between the respective devices that isolates electromagnetic energy coupling from one device to another.

Abstract: The present invention describes systems and methods for providing high-density capacitors. An exemplary embodiment of the present invention provides a high-density capacitor system comprising a substrate and a porous conductive layer formed on the substrate, wherein the porous conductive layer is formed in accordance with a predetermined pattern. Furthermore, the high-density capacitor system includes a dielectric material formed on the porous conductive layer and a second conductive layer formed on the dielectric material. Additionally, the high-density capacitor system includes a plurality of conductive pads configured in communication with the second conductive layer.

Abstract: The present invention describes systems and methods for fabricating high-density capacitors. An exemplary embodiment of the present invention provides a method for fabricating a high-density capacitor system including the steps of providing a substrate and depositing a nanoelectrode particulate paste layer onto the substrate. The method for fabricating a high-density capacitor system further includes sintering the nanoelectrode particulate paste layer to form a bottom electrode. Additionally, the method for fabricating a high-density capacitor system includes depositing a dielectric material onto the bottom electrode with an atomic layer deposition process. Furthermore, the method for fabricating a high-density capacitor system includes depositing a conductive material on the dielectric material to form a top electrode.

Abstract: Disclosed are ferroelectric and ferromagnetic noise isolation structures that reduce electromagnetic interference and noise in integrated circuit devices and system architectures. Representative structures comprise two or more devices that are vertically disposed relative to one another, and a thin ferroelectric or ferromagnetic film layer disposed between the respective devices that isolates electromagnetic energy coupling from one device to another.

Abstract: Disclosed are three-dimensional dielectric structures on high surface area electrodes and fabrication methods. Exemplary structures comprise a copper foil substrate, trench electrodes or high surface area porous electrode structures formed on the substrate, a insulating thin film formed on the surface and laminating the foil on a organic substrate. A variety of materials may be used to make the films including perovksite ceramics such as barium titanate, strontium titanate, barium strontium titanate (BST), lead zirconate titanate (PZT); other intermediate dielectric constant films such as zinc oxide, aluminum nitride, silicon nitride; typical paraelectrics such as tantalum oxide, alumina, and titania. The films may be fabricated using sol-gel, hydrothermal synthesis, anodization or vapor deposition techniques.

Abstract: Disclosed are any electronic system or module which includes embedded actives and discrete passives, and methods for use in fabricating packages containing embedded active devices and/or discrete passive devices. Exemplary apparatus comprises a plurality of build-up layers defining circuit interconnections and that comprise one or more thin film type of embedded passive devices, at least a cavity formed in the build-up layers, and at least an active device and/or at least a discrete passive device disposed in the cavity and electrically connected to the circuit interconnections of the build-up layers. A stiffener may be coupled to an exposed (back) surface of the active device and to an adjacent surface of the build-up layers. The build-up layers may be mounted to a core, and the core may be attached to a printed circuit board. Alternatively, a bottom surface of the build-up layers may be mounted to a printed circuit board without core.

Abstract: Disclosed are organic-compatible thin film processing techniques with reactive (such as Ti) layers for embedding capacitors into substrates. Hydrothermal synthesis allows direct deposition of high-k films with capacitance density of about 1 ?F/cm2 on organic substrates. This is done by reactively growing a high-k film from Ti foil/Ti-coated copper foil/Ti precursor-coated organic substrate in an alkaline barium ion bath. Alternatives may be used to address multiple coatings, low temperature baking, low temperature pyrolysis with oxygen plasma, etc. Sol-gel and RF-sputtering assisted by a reaction with the intermediate layer and a foil transfer process may be used to integrate perovskite thin films with a capacitance in the range of 1-5 ?F/cm2. Thermal oxidation of titanium foil/Ti-coated copper foil/Ti-coated organic substrate with a copper conductive layer is also a reactively grown high-k film process for integrating capacitance of hundreds of nF with or without using a foil transfer process.

Abstract: Disclosed are composite RF devices having low temperature coefficient of permittivity (TCP) and methods for fabricating same. The RF devices comprise first and second conductive electrodes with a composite dielectric material disposed there between that comprises a polymer material having positive or negative TCP and one or more ceramic filler materials having corresponding negative or positive temperature coefficients of permittivity. The composite dielectric material may also comprise a blend of positive and negative TCP ceramic filler materials. The composite dielectric material may also have a bimodal distribution of positive and negative TCP filler materials to vary the packing density of the dielectric material. Various devices may be fabricated including thin and thick film capacitors and antennas, which may be formed on or within an organic layer, silicon material, ceramic material, ceramic composite material or insulating material.

Abstract: Disclosed are methods and substrates suitable for flip-chip assembly. Underfill processing used to produce the substrates provides for lead-free, eutectic solder, and other alloy reflow based flip-chip interconnects for 10-20 ?m peripheral and area array I/O pitch. The methods and substrates utilize underfill materials with tailored properties along with a variety of patterning techniques to produce openings in underfill material disposed on the substrates that are used as an alignment guide for flip-chip attachment to the substrates.

Abstract: Nano-structured interconnect formation and a reworkable bonding process using solder films. Large area fabrication of nano-structured interconnects is demonstrated at a very fine pitch. This technology can be used for pushing the limits of current flip chip bonding in terms of pitch, number of I/Os, superior combination of electrical and mechanical properties as well as reworkability. Sol-gel and electroless processes were developed to demonstrate film bonding interfaces between metallic pads and nano interconnects. Solution-derived nano-solder technology is an attractive low-cost method for several applications such as MEMS hermetic packaging, compliant interconnect bonding and bump-less nano-interconnects.

Abstract: A low-temperature process that combines high-aspect-ratio polymer structures with electroless copper plating to create laterally compliant MEMS structures. These structures can be used as IC-package interconnects that can lead to reliable, low-cost and high-performance nano wafer-level packaging. High-aspect-ratio low CTE polyimide structures with low stress, high toughness and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80 degrees leading to an aspect ratio higher than 4. The etching process also leads to roughened sidewalls for selective electroless plating on the sidewalls of the polymer structures. These fabricated structures show reduction in the stresses at the interfaces and superior reliability as IC-package nano interconnects. Metal-coated polymer structures from MEMS fabrication techniques can provide low-cost high-performance solutions for wafer-level-packaging.