Patents by Inventor Rao Yalamanchili
Rao Yalamanchili has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11915932Abstract: Exemplary etching methods may include forming a plasma of a fluorine-containing precursor to produce plasma effluents. A first bias frequency may be applied while forming the plasma. The methods may include contacting a substrate housed in a processing region of a semiconductor processing chamber with the plasma effluents. The substrate may be or include a photomask. The methods may include etching a first layer of the photomask. Etching the first layer of the photomask may expose a second layer of the photomask. The methods may include adjusting the first bias frequency to a second bias frequency while maintaining the plasma of the fluorine-containing precursor. The methods may include etching the second layer of the photomask.Type: GrantFiled: April 28, 2021Date of Patent: February 27, 2024Assignee: Applied Materials, Inc.Inventors: Toi Yue Becky Leung, Madhavi Rajaram Chandrachood, Madhava Rao Yalamanchili
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Publication number: 20230207393Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.Type: ApplicationFiled: March 2, 2023Publication date: June 29, 2023Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, James M. Holden
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Patent number: 11621194Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.Type: GrantFiled: December 29, 2020Date of Patent: April 4, 2023Assignee: Applied Materials, Inc.Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, James M. Holden
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Publication number: 20220351972Abstract: Exemplary etching methods may include forming a plasma of a fluorine-containing precursor to produce plasma effluents. A first bias frequency may be applied while forming the plasma. The methods may include contacting a substrate housed in a processing region of a semiconductor processing chamber with the plasma effluents. The substrate may be or include a photomask. The methods may include etching a first layer of the photomask. Etching the first layer of the photomask may expose a second layer of the photomask. The methods may include adjusting the first bias frequency to a second bias frequency while maintaining the plasma of the fluorine-containing precursor. The methods may include etching the second layer of the photomask.Type: ApplicationFiled: April 28, 2021Publication date: November 3, 2022Applicant: Applied Materials, Inc.Inventors: Toi Yue Becky Leung, Madhavi Rajaram Chandrachood, Madhava Rao Yalamanchili
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Publication number: 20210134676Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.Type: ApplicationFiled: December 29, 2020Publication date: May 6, 2021Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, James M. Holden
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Patent number: 10910271Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.Type: GrantFiled: May 27, 2020Date of Patent: February 2, 2021Assignee: Applied Materials, Inc.Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, James M. Holden
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Publication number: 20200286787Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.Type: ApplicationFiled: May 27, 2020Publication date: September 10, 2020Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, James M. Holden
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Patent number: 10714390Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.Type: GrantFiled: December 6, 2019Date of Patent: July 14, 2020Assignee: Applied Materials, Inc.Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, James M. Holden
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Publication number: 20200118880Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.Type: ApplicationFiled: December 6, 2019Publication date: April 16, 2020Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, James M. Holden
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Patent number: 10566238Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.Type: GrantFiled: November 16, 2018Date of Patent: February 18, 2020Assignee: Applied Materials, Inc.Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, James M. Holden
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Publication number: 20190088549Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.Type: ApplicationFiled: November 16, 2018Publication date: March 21, 2019Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, James M. Holden
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Patent number: 10163713Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.Type: GrantFiled: January 25, 2016Date of Patent: December 25, 2018Assignee: Applied Materials, Inc.Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, James M. Holden
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Patent number: 10147531Abstract: The present disclosure includes an electrical power transformer that may include a core and a conductor pack. A conductor pack may include a conducting layer disposed around a portion of the core, a first planar insulating layer disposed on a first side of the conducting layer, and a second planar insulating layer disposed on a second side of the conducting layer. A cooling member may be disposed adjacent to the conductor pack. A method of manufacturing an electrical power transformer may include providing a core and providing a plurality of planar conductor packs. The planar conductor packs including a plurality of planar conducting layers and a plurality of planar insulating layers. The method may include inserting a cooling member between insulating layers of adjacent ones of the plurality of planar conductor packs.Type: GrantFiled: April 8, 2015Date of Patent: December 4, 2018Assignee: Lear CorporationInventors: Rutunj Rai, Venkat Rao Yalamanchili, Parminder Brar, Michael Scott Duco
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Patent number: 9620379Abstract: Methods of dicing substrates having a plurality of ICs. A method includes forming a multi-layered mask comprising a laser energy absorbing, non-photodefinable topcoat disposed over a water-soluble base layer disposed over the semiconductor substrate. Because the laser light absorbing material layer is non-photodefinable, material costs associated with conventional photo resist formulations may be avoided. The mask is direct-write patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. Absorption of the mask layer within the laser emission band (e.g., UV band and/or green band) promotes good scribe line quality. The substrate may then be plasma etched through the gaps in the patterned mask to singulate the IC with the mask protecting the ICs during the plasma etch. The soluble base layer of the mask may then be dissolved subsequent to singulation, facilitating removal of the layer.Type: GrantFiled: March 11, 2014Date of Patent: April 11, 2017Assignee: Applied Materials, Inc.Inventors: Wei-Sheng Lei, Mohammad Kamruzzaman Chowdhury, Todd Egan, Brad Eaton, Madhava Rao Yalamanchili, Ajay Kumar
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Patent number: 9465677Abstract: A partitioned application environment is disclosed. In various embodiments, a request associated with an application environment in which an application is running is received from the application. A determination is made to fulfill the request at least in part via a call to a node at which application code associated with the application is running in an application environment partition provided at the node. A call associated with the request is sent to the node, based at least in part on the determination.Type: GrantFiled: March 31, 2016Date of Patent: October 11, 2016Assignee: MOBILE IRON, INC.Inventors: Aaditya Chandrasekhar, Maksim Orlovich, Rama Rao Yalamanchili, Lawrence Lee, Jack Wu
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Publication number: 20160254085Abstract: The present disclosure includes an electrical power transformer that may include a core and a conductor pack. A conductor pack may include a conducting layer disposed around a portion of the core, a first planar insulating layer disposed on a first side of the conducting layer, and a second planar insulating layer disposed on a second side of the conducting layer. A cooling member may be disposed adjacent to the conductor pack. A method of manufacturing an electrical power transformer may include providing a core and providing a plurality of planar conductor packs. The planar conductor packs including a plurality of planar conducting layers and a plurality of planar insulating layers. The method may include inserting a cooling member between insulating layers of adjacent ones of the plurality of planar conductor packs.Type: ApplicationFiled: April 8, 2015Publication date: September 1, 2016Inventors: Rutunj Rai, Venkat Rao Yalamanchili, Parminder Brar, Michael Scott Duco
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Publication number: 20160217019Abstract: A partitioned application environment is disclosed. In various embodiments, a request associated with an application environment in which an application is running is received from the application. A determination is made to fulfill the request at least in part via a call to a node at which application code associated with the application is running in an application environment partition provided at the node. A call associated with the request is sent to the node, based at least in part on the determination.Type: ApplicationFiled: March 31, 2016Publication date: July 28, 2016Inventors: Aaditya Chandrasekhar, Maksim Orlovich, Rama Rao Yalamanchili, Lawrence Lee, Jack Wu
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Patent number: 9348678Abstract: A partitioned application environment is disclosed. In various embodiments, a request associated with an application environment in which an application is running is received from the application. A determination is made to fulfill the request at least in part via a call to a node at which application code associated with the application is running in an application environment partition provided at the node. A call associated with the request is sent to the node, based at least in part on the determination.Type: GrantFiled: June 19, 2013Date of Patent: May 24, 2016Assignee: MOBILE IRON, INC.Inventors: Aaditya Chandrasekhar, Maksim Orlovich, Rama Rao Yalamanchili, Lawrence Lee, Jack Wu
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Publication number: 20160141210Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to for corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.Type: ApplicationFiled: January 25, 2016Publication date: May 19, 2016Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, James M. Holden
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Patent number: 9280051Abstract: Methods for reducing line width roughness and/or critical dimension nonuniformity in a photoresist pattern are provided herein. In some embodiments, a method of reducing line width roughness along a sidewall of a patterned photoresist layer disposed atop a substrate includes: (a) depositing a first layer atop the sidewall of the patterned photoresist layer; (b) etching the first layer and the sidewall after depositing the first layer to reduce the line width roughness of the patterned photoresist layer. In some embodiments, (a)-(b) may be repeated until the line width roughness is substantially smooth.Type: GrantFiled: June 11, 2014Date of Patent: March 8, 2016Assignee: APPLIED MATERIALS, INC.Inventors: Banqiu Wu, Ajay Kumar, Rao Yalamanchili, Omkaram Nalamasu