Patents by Inventor Raoji A. Patel
Raoji A. Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7193410Abstract: A monitor system and method are described for sensing voltage changes in a plurality of transistors of a multiphase circuit comprising a sensor connected to each one of the plurality of transistors for measuring a voltage drop across the each one, a difference detector for comparing the voltage drop to a previous voltage drop attributable to the each one of the plurality of transistors, and a driver circuit for controlling a state of the plurality of transistors, wherein the driver circuit deactivates one or more of the plurality of transistors when the voltage drop varies from the previous voltage drop by a predefined amount.Type: GrantFiled: May 4, 2004Date of Patent: March 20, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Raoji A. Patel, Robert A. Guenther
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Patent number: 6831544Abstract: A method and apparatus to layout planar magnetic coils on a PCB consists of maximizing the layer to layer overlap, and consequently maximizing total inductance for the given layout area, by spiraling alternating layers inward and outward. A further benefit of the matching opposite spirals is the ability to make the layer to layer electrical contacts within the magnetic field area, thus reducing leakage inductance, and minimizing the wasted extra conductor line length needed to make the connections outside the magnetic field. The reduced conductor line length results in reduced conductor line resistance. The method is applicable to voltage transformers and isolation transformers as well as simple inductors and other magnetic devices. In the transformer case the odd numbered layers are typically connected together in series to provide a larger turn ratio, and the even numbered layers are typically single turns (i.e., no spiral) connected together in parallel to provide more current capability.Type: GrantFiled: October 9, 2003Date of Patent: December 14, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Raoji A. Patel, James E. Drew, Raymond A. Pelletier, Brian R. McQuain
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Publication number: 20040070481Abstract: A method and apparatus to layout planar magnetic coils on a PCB consists of maximizing the layer to layer overlap, and consequently maximizing total inductance for the given layout area, by spiraling alternating layers inward and outward. A further benefit of the matching opposite spirals is the ability to make the layer to layer electrical contacts within the magnetic field area, thus reducing leakage inductance, and minimizing the wasted extra conductor line length needed to make the connections outside the magnetic field. The reduced conductor line length results in reduced conductor line resistance. The method is applicable to voltage transformers and isolation transformers as well as simple inductors and other magnetic devices. In the transformer case the odd numbered layers are typically connected together in series to provide a larger turn ratio, and the even numbered layers are typically single turns (i.e., no spiral) connected together in parallel to provide more current capability.Type: ApplicationFiled: October 9, 2003Publication date: April 15, 2004Inventors: Raoji A. Patel, James E. Drew, Raymond A. Pelletier, Brian R. McQuain
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Patent number: 6664883Abstract: A method and apparatus to layout planar magnetic coils on a PCB consists of maximizing the layer to layer overlap, and consequently maximizing total inductance for the given layout area, by spiraling alternating layers inward and outward. A further benefit of the matching opposite spirals is the ability to make the layer to layer electrical contacts within the magnetic field area, thus reducing leakage inductance, and minimizing the wasted extra conductor line length needed to make the connections outside the magnetic field. The reduced conductor line length results in reduced conductor line resistance. The method is applicable to voltage transformers and isolation transformers as well as simple inductors and other magnetic devices. In the transformer case the odd numbered layers are typically connected together in series to provide a larger turn ratio, and the even numbered layers are typically single turns (i.e., no spiral) connected together in parallel to provide more current capability.Type: GrantFiled: June 11, 2002Date of Patent: December 16, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventors: Raoji A. Patel, James E. Drew, Raymond A. Pelletier, Brian R. McQuain
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Patent number: 6600668Abstract: A crowbar circuit comprises an over-voltage detector that monitors the output voltage of a synchronous DC/DC converter. When the output voltage rises above a predetermined threshold, the detector applies a control signal to a MOSFET switch that is already in use as part of a rectifier in the converter. The control signal overrides a periodic switching signal applied to the gate of the MOSFET, causing it to conduct continuously and thereby apply a shunt path for the output current of the rectifier. The control signal may be continuously applied until the converter is manually reset. Because the voltage across the conducting MOSFET is small and it can be turned on quickly, the MOSFET rapidly clamps the DC/DC converter's output to a voltage low enough to avoid damage to integrated circuitry powered by the converter.Type: GrantFiled: May 21, 2002Date of Patent: July 29, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventors: Raoji A. Patel, Raymond A. Pelletier
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Patent number: 6565382Abstract: A core mounting assembly includes a printed wiring board having a substrate with opposite sides, a winding on one side and a plurality of through holes extending through the substrate adjacent to the winding. A pair of mirror-image core sections are positioned against the sides of the board opposite the first winding, the core sections having corresponding portions which project into the through holes. A bracket has a back portion engaging one of the core sections and at least two legs extending from the back portion through two of the through holes in the board. A resilient cover member has a first end releasably secured to one of the legs, a second end releasably secured to the other of the legs and a bridging portion extending between the first and second ends and pressing against the other of the core sections so as to bias the core sections together.Type: GrantFiled: December 7, 2001Date of Patent: May 20, 2003Assignee: Hewelett-Packard Development Company, L.P.Inventors: William M. Blodgett, Richard E. Olson, Raoji A. Patel
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Publication number: 20020149461Abstract: A method and apparatus to layout planar magnetic coils on a PCB consists of maximizing the layer to layer overlap, and consequently maximizing total inductance for the given layout area, by spiraling alternating layers inward and outward. A further benefit of the matching opposite spirals is the ability to make the layer to layer electrical contacts within the magnetic field area, thus reducing leakage inductance, and minimizing the wasted extra conductor line length needed to make the connections outside the magnetic field. The reduced conductor line length results in reduced conductor line resistance. The method is applicable to voltage transformers and isolation transformers as well as simple inductors and other magnetic devices. In the transformer case the odd numbered layers are typically connected together in series to provide a larger turn ratio, and the even numbered layers are typically single turns (i.e., no spiral) connected together in parallel to provide more current capability.Type: ApplicationFiled: June 11, 2002Publication date: October 17, 2002Applicant: Compaq Computer CorporationInventors: Raoji A. Patel, James E. Drew, Raymond A. Pelletier, Brian R. McQuain
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Patent number: 6429763Abstract: A method and apparatus to layout planar magnetic coils on a PCB consists of maximizing the layer to layer overlap, and consequently maximizing total inductance for the given layout area, by spiraling alternating layers inward and outward. A further benefit of the matching opposite spirals is the ability to make the layer to layer electrical contacts within the magnetic field area, thus reducing leakage inductance, and minimizing the wasted extra conductor line length needed to make the connections outside the magnetic field. The reduced conductor line length results in reduced conductor line resistance. The method is applicable to voltage transformers and isolation transformers as well as simple inductors and other magnetic devices. In the transformer case the odd numbered layers are typically connected together in series to provide a larger turn ratio, and the even numbered layers are typically single turns (i.e., no spiral) connected together in parallel to provide more current capability.Type: GrantFiled: February 1, 2000Date of Patent: August 6, 2002Assignee: Compaq Information Technologies Group, L.P.Inventors: Raoji A. Patel, James E. Drew, Raymond A. Pelletier, Brian R. McQuain
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Publication number: 20020057171Abstract: A method and apparatus to layout planar magnetic coils on a PCB consists of maximizing the layer to layer overlap, and consequently maximizing total inductance for the given layout area, by spiraling alternating layers inward and outward. A further benefit of the matching opposite spirals is the ability to make the layer to layer electrical contacts within the magnetic field area, thus reducing leakage inductance, and minimizing the wasted extra conductor line length needed to make the connections outside the magnetic field. The reduced conductor line length results in reduced conductor line resistance. The method is applicable to voltage transformers and isolation transformers as well as simple inductors and other magnetic devices. In the transformer case the odd numbered layers are typically connected together in series to provide a larger turn ratio, and the even numbered layers are typically single turns (i.e., no spiral) connected together in parallel to provide more current capability.Type: ApplicationFiled: February 1, 2000Publication date: May 16, 2002Inventors: Raoji A. Patel, James E. Drew, Raymond A. Pelletier, Brian R. McQuain
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Patent number: 6373732Abstract: A method of preventing current hogging in parallel connected transformers, and an apparatus for efficiently implementing the method are presented. Current hogging occurs when synchronous power converter transformers operate in a low output current mode. Low output current demands are typically meet by adjusting the duty cycle of the transformer to a low level. This results in the catch FET maintaining a low resistance path to ground for long time periods and allows a stronger one of the parallel power converter transformers to sink current to ground through a weaker transformer. The method consists of using a current sensor to detect low or negative output currents, and then driving the transistor providing the path to ground to an off state.Type: GrantFiled: February 1, 2000Date of Patent: April 16, 2002Assignee: Compaq Information Technologies Group, L.P.Inventors: Raoji A. Patel, Raymond A. Pelletier, Robert J. Wolf