Patents by Inventor Raphaël Riva

Raphaël Riva has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10847494
    Abstract: Some embodiments are directed to a method of determining a sintering thermal impedance of a sintering layer by: providing a substrate having a predetermined substrate thermal impedance and disposing the sintering layer on the substrate forming with the sintering layer a stack. Placing at least one semiconductor die, that includes a semiconductor element with at least two element electrodes on the sintering layer. Injecting an electrical current through the at least two element electrodes for measuring a temperature sensitive parameter of the semiconductor element. Heating the stack with a predetermined heat power and determining, while sintering, a semiconductor element temperature from the measured temperature sensitive parameter.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: November 24, 2020
    Assignees: AGILE POWER SWITCH 3D-INTEGRATION APSI3D, IRT SAINT EXUPERY (AESE), ECOLE NATIONALE D'INGENIEURS DE TARBES
    Inventors: Jacques Pierre Henri Favre, Jean-Michel Francis Reynes, Raphaël Riva, Paul-Etienne Joseph Vidal, Baptiste Louis Jean Trajin
  • Publication number: 20200043885
    Abstract: A method of determining a sintering thermal impedance of a sintering layer (25) comprising: providing a substrate (20) having a predetermined substrate thermal impedance, disposing the sintering layer (25) on the substrate (20) forming with the sintering layer (25) a stack, placing at least one semiconductor die (30) comprising a semiconductor element (40) with at least two element electrodes (45; 47) on the sintering layer (25), injecting an electrical current through the at least two element electrodes (45; 47) for measuring a temperature sensitive parameter of the semiconductor element (40), heating the stack with a predetermined heat power, determining, while sintering, a semiconductor element temperature from the measured temperature sensitive parameter, measuring a stack temperature, determining a stack thermal impedance by subtracting the semiconductor element temperature from the stack temperature and dividing by the predetermined heat power, and subtracting the predetermined substrate thermal impedan
    Type: Application
    Filed: October 2, 2017
    Publication date: February 6, 2020
    Inventors: Jacques Pierre Henri FAVRE, Jean-Michel Francis REYNES, Raphaël RIVA, Paul-Etienne Joseph VIDAL, Baptiste Louis Jean TRAJIN
  • Patent number: 10332828
    Abstract: Some embodiments relate to a semiconductor power device that includes a first substrate, a second substrate, a stack and an interconnect structure. The first substrate includes a first patterned electrically conductive layer on a first surface and a switching semiconductor element. The second substrate includes a second surface facing the first surface and a second patterned electrically conductive layer on the second surface. The stack includes an electrically conductive track and a layer of a dielectric material. The layer of the dielectric material is provided on the first or second patterned electrically conductive layer and the layer of the dielectric material isolates the electrically conductive track from the patterned electrically conductive layer on which the stack is provided. The interconnect structure provides at least one electrical connection electrically conductive layers or areas of the substrates.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: June 25, 2019
    Assignees: AGILE POWER SWITCH 3D—INTEGRATION APSI3D, IRT SAINT EXUPERY (AESE)
    Inventors: Jacques Pierre Henri Favre, Jean-Michel Francis Reynes, Raphaël Riva, Bernard José Charles Du Trieu De Terdonck
  • Publication number: 20180277475
    Abstract: Some embodiments relate to a semiconductor power device that includes a first substrate, a second substrate, a stack and an interconnect structure. The first substrate includes a first patterned electrically conductive layer on a first surface and a switching semiconductor element. The second substrate includes a second surface facing the first surface and a second patterned electrically conductive layer on the second surface. The stack includes an electrically conductive track and a layer of a dielectric material. The layer of the dielectric material is provided on the first or second patterned electrically conductive layer and the layer of the dielectric material isolates the electrically conductive track from the patterned electrically conductive layer on which the stack is provided. The interconnect structure provides at least one electrical connection electrically conductive layers or areas of the substrates.
    Type: Application
    Filed: September 30, 2015
    Publication date: September 27, 2018
    Inventors: Jacques Pierre Henri FAVRE, Jean-Michel Francis REYNES, Raphaël RIVA, Bernard José Charles DU TRIEU DE TERDONCK
  • Publication number: 20130297040
    Abstract: The present invention relates to an implant comprising: —a core material comprising polydimethylsiloxane or at least one hydrogel polymer; —a tube encasing said core material comprising an ethylene vinyl acetate polymer or at least one hydrogel polymer; —a sealant for closure of the open ends of said tube comprising polydimethylsiloxane or a mono-, di-, or triacetoxy derivative thereof, or at least one hydrogel polymer; and —at least one active ingredient; wherein said at least one active ingredient is selected from the group comprising celecoxib, sulindac, tamoxifen, oestrogen, oestradiol, ethinyl oestradiol, mestranol, dienogest, norgestrel, levonorgestrel, desogestrel, norgestimate, ethynodiol diacetate, leuprorelin, buserelin, gonrelin, triptorelin, nafarelin, deslorelin, histrelin, and supprelin; and with the proviso that when the sealant is said at least one hydrogelpolymer, the core material comprises polydimethylsiloxane. Furthermore, the invention relates to an implant for use as a medicament.
    Type: Application
    Filed: January 16, 2012
    Publication date: November 7, 2013
    Applicants: UNIVERSITE DE LIEGE, UNIVERSITE CATHOLIQUE DE LOUVAIN
    Inventors: Jacques Donnez, Anne Van Langendonkt, Sylvie Defrère, Jean-Michel Foidart, Christine Jérome, Brigitte Evrard, Raphaël Riva, Fabrice Krier, Mélanie Mestdagt