Abstract: The present disclosure provides an integrated circuit comprising a memory controller configured to transmit information stored in a memory to a processing unit. An example memory controller includes an error detection circuit configured to detect an error in the information by implementing an error correcting code algorithm, and to generate an interrupt signal in the event of detection of at least one error in the information and a transmission control circuit configured to transmit the interrupt signal to the processing unit only when the error is detected for the first time in the information by the error detection circuit.

Abstract: A memory system includes a memory with memory blocks. A first logic circuit performs an XOR combinational logic function of a current value of a data addressing mode and of at least one bit of a first data packet including an error correction code of a data element to be written. A second data packet, generated by the first logic circuit, is stored into one of the memory blocks. A second logic circuit performs an XOR combinational logic function of at least one bit of the second packet (such as read from one of the memory blocks) and of the current value of the addressing mode. A weight of the bit of the first data packet corresponds to a weight of the at least one bit of the second read data packet.

Abstract: A method of protecting a microcontroller is provided. An example method comprises a personalization phase and a boot phase. A personalization phase comprises: the calculation of a first checksum on the content of at least one configuration register of the microcontroller stored in a first memory, and the storage, into the first memory, of the first checksum; and the copying of the first checksum and of the register to a second memory. A boot phase comprises: the copying of the first checksum and of the register from the second memory to the first memory; and the comparison between a second checksum, calculated on the content of the copied register, and the copied first checksum.

Abstract: The present disclosure provides an integrated circuit comprising a memory controller configured to transmit information stored in a memory to a processing unit. An example memory controller includes an error detection circuit configured to detect an error in the information by implementing an error correcting code algorithm, and to generate an interrupt signal in the event of detection of at least one error in the information and a transmission control circuit configured to transmit the interrupt signal to the processing unit only when the error is detected for the first time in the information by the error detection circuit.

Abstract: A memory system includes a memory with memory blocks. A first logic circuit performs an XOR combinational logic function of a current value of a data addressing mode and of at least one bit of a first data packet including an error correction code of a data element to be written. A second data packet, generated by the first logic circuit, is stored into one of the memory blocks. A second logic circuit performs an XOR combinational logic function of at least one bit of the second packet (such as read from one of the memory blocks) and of the current value of the addressing mode. A weight of the bit of the first data packet corresponds to a weight of the at least one bit of the second read data packet.