Abstract: A multi-core processor, comprising a plurality of processor cores to process jobs, a multicore navigator coupled to the plurality of processor cores to evaluate a job for atomicity and, based on determining the job to have atomicity, to determine whether there is an atomic wait queue associated with the job's atomicity. Based on there being an atomic wait queue associated with the job's atomicity, the multicore navigator is to push the job to the atomic wait queue.

Abstract: A multi-core processor, comprising a plurality of processor cores to process jobs, a multicore navigator coupled to the plurality of processor cores to evaluate a job for atomicity and, based on determining the job to have atomicity, to determine whether there is an atomic wait queue associated with the job's atomicity. Based on there being an atomic wait queue associated with the job's atomicity, the multicore navigator is to push the job to the atomic wait queue.

Abstract: Apparatus and method for providing correlation in a CDMA receiver. A Generic Correlation Coprocessor comprises one or more correlation blocks. Each correlation block comprises a correlation input buffer coupled to one or more correlators. The correlators are coupled to an interpolator input buffer and to a correlator output buffer. One or more interpolators are coupled to the interpolation input buffer and to the correlation output buffer. The correlators correlate the received signal with PN codes to produce a correlated signal. The correlated signal is stored in the correlator output buffer and/or the interpolation input buffer, and provided from the interpolation input buffer to the one or more interpolators. The one or more interpolators interpolate the correlated signal to produce an interpolated signal. The interpolated signal is stored in the correlator output buffer. Signals are provided from the correlator output buffer to other receiver processing systems.

Abstract: Apparatus and method for providing correlation in a CDMA receiver. A Generic Correlation Coprocessor comprises one or more correlation blocks. Each correlation block comprises a correlation input buffer coupled to one or more correlators. The correlators are coupled to an interpolator input buffer and to a correlator output buffer. One or more interpolators are coupled to the interpolation input buffer and to the correlation output buffer. The correlators correlate the received signal with PN codes to produce a correlated signal. The correlated signal is stored in the correlator output buffer and/or the interpolation input buffer, and provided from the interpolation input buffer to the one or more interpolators. The one or more interpolators interpolate the correlated signal to produce an interpolated signal. The interpolated signal is stored in the correlator output buffer. Signals are provided from the correlator output buffer to other receiver processing systems.

Abstract: Apparatus and method for providing correlation in a CDMA receiver. A Generic Correlation Coprocessor comprises one or more correlation blocks. Each correlation block comprises a correlation input buffer coupled to one or more correlators. The correlators are coupled to an interpolator input buffer and to a correlator output buffer. One or more interpolators are coupled to the interpolation input buffer and to the correlation output buffer. The correlators correlate the received signal with PN codes to produce a correlated signal. The correlated signal is stored in the correlator output buffer and/or the interpolation input buffer, and provided from the interpolation input buffer to the one or more interpolators. The one or more interpolators interpolate the correlated signal to produce an interpolated signal. The interpolated signal is stored in the correlator output buffer. Signals are provided from the correlator output buffer to other receiver processing systems.

Abstract: Apparatus and method for providing correlation in a CDMA receiver. A Generic Correlation Coprocessor comprises one or more correlation blocks. Each correlation block comprises a correlation input buffer coupled to one or more correlators. The correlators are coupled to an interpolator input buffer and to a correlator output buffer. One or more interpolators are coupled to the interpolation input buffer and to the correlation output buffer. The correlators correlate the received signal with PN codes to produce a correlated signal. The correlated signal is stored in the correlator output buffer and/or the interpolation input buffer, and provided from the interpolation input buffer to the one or more interpolators. The one or more interpolators interpolate the correlated signal to produce an interpolated signal. The interpolated signal is stored in the correlator output buffer. Signals are provided from the correlator output buffer to other receiver processing systems.

Abstract: A Viterbi decoder system is provided in accordance with the present invention. The decoder system includes a State Metric Update unit including a state metric memory and a cascaded Add/Compare/Select (ACS) unit. The cascaded ACS unit comprises a plurality of serially coupled ACS stages for performing a plurality of ACS operations in conjunction with the state metric memory. An ACS stage is operable to identify a plurality of path decisions and path differences and communicate the identified path decisions and the identified path differences to a next ACS stage coupled thereto. The decoder also includes a Traceback unit for storing a set of accumulated path decisions in a traceback memory associated therewith, and performing a traceback on the set of accumulated path decisions. The path decisions associated with the ACS stage and the next ACS stage are accumulated as a set during the ACS operations before being written to the traceback memory, thereby minimizing accesses to the traceback memory.

Abstract: A Viterbi decoder system is provided in accordance with the present invention. The decoder system includes a State Metric Update unit including a state metric memory and a cascaded Add/Compare/Select (ACS) unit. The cascaded ACS unit comprises a plurality of serially coupled ACS stages for performing a plurality of ACS operations in conjunction with the state metric memory. An ACS stage is operable to identify a plurality of path decisions and path differences and communicate the identified path decisions and the identified path differences to a next ACS stage coupled thereto. The decoder also includes a Traceback unit for storing a set of accumulated path decisions in a traceback memory associated therewith, and performing a traceback on the set of accumulated path decisions. The path decisions associated with the ACS stage and the next ACS stage are accumulated as a set during the ACS operations before being written to the traceback memory, thereby minimizing accesses to the traceback memory.