Abstract: A system comprises a superconducting quantizing inductor and superconducting control circuitry, which is coupled to the superconducting quantizing inductor to form a superconducting loop, and which is configured to selectively inject a quantized amount of positive or negative current into the superconducting loop to generate a quantized circulating current in the superconducting loop. The quantized circulating current comprises a time-varying or static circulating current. The superconducting control circuitry comprises first and second current generator circuits which comprise a first and second plurality of Josephson junctions, respectively, which are configured to inject quantized amounts of positive current and negative current into the superconducting loop in response to single flux quantum pulses.

Abstract: A system comprises a superconducting quantizing inductor and superconducting control circuitry, which is coupled to the superconducting quantizing inductor to form a superconducting loop, and which is configured to selectively inject a quantized amount of positive or negative current into the superconducting loop to generate a quantized circulating current in the superconducting loop. The quantized circulating current comprises a time-varying or static circulating current. The superconducting control circuitry comprises first and second current generator circuits which comprise a first and second plurality of Josephson junctions, respectively, which are configured to inject quantized amounts of positive current and negative current into the superconducting loop in response to single flux quantum pulses.

Abstract: A design-for-test (DFT) architecture for testing a three dimensional (3D) integrated circuit, may comprise a two dimensional (2D) silicon layer n?1 and a 2D silicon layer n connected together with a through silicon via (TSV) having a first side and a second side; scannable latch circuits on said first side and said second side of said TSV, wherein said scannable latch circuits: control flow of data between said layer n?1 and said layer n and allow said TSV to be verified; allow launch and capture clocks to be applied with variable delay in order to perform an alternating current delay fault test between said layer n?1 and said layer n; and have a quiescent state supply current (IDDq) test function built in which allows selection of an input load for a unidirectional signal connection between said layer n?1 and said layer n.

Abstract: Testing of a three-dimensional (3D) integrated circuit includes defining a first group of parts by a region and/or layer on the 3D integrated circuit. The testing further includes applying a first intensity of stress test conditions to the first group of parts. The testing also includes defining a second group of parts by a region and/or layer on the 3D integrated circuit that is different from the first group of parts. The testing further includes and applying a second intensity of stress test conditions to the second group of parts. The second intensity of stress test conditions is greater than the first intensity and is determined by sensitivities identified for each of the first and second group of parts. A determination is made whether the 3D integrated circuit passed the testing based upon results of application of the first and second intensities of stress test conditions.

Abstract: Noise reduction for application of structural test patterns to a Device Under Test (DUT) is accomplished with a capacitor “booster” bypass network on the probe card in which the capacitors are charged to a much higher voltage Vboost than the DUT power supply voltage VDD. Charging the capacitors to a voltage N×VDD allows the buster network to store N times the charge of a conventionally configured capacitance network, and effectively provides N times the capacitance of the original network in the same physical space.

Abstract: Noise reduction for application of structural test patterns to a Device Under Test (DUT) is accomplished with a capacitor “booster” bypass network on the probe card in which the capacitors are charged to a much higher voltage Vboost than the DUT power supply voltage VDD. Charging the capacitors to a voltage N×VDD allows the buster network to store N times the charge of a conventionally configured capacitance network, and effectively provides N times the capacitance of the original network in the same physical space.

Abstract: Noise reduction for application of structural test patterns to a Device Under Test (DUT) is accomplished with a capacitor “booster” bypass network on the probe card in which the capacitors are charged to a much higher voltage Vboost than the DUT power supply voltage VDD. Charging the capacitors to a voltage N×VDD allows the buster network to store N times the charge of a conventionally configured capacitance network, and effectively provides N times the capacitance of the original network in the same physical space.

Abstract: Noise reduction for application of structural test patterns to a Device Under Test (DUT) is accomplished with a capacitor “booster” bypass network on the probe card in which the capacitors are charged to a much higher voltage Vboost than the DUT power supply voltage VDD. Charging the capacitors to a voltage N×VDD allows the buster network to store N times the charge of a conventionally configured capacitance network, and effectively provides N times the capacitance of the original network in the same physical space.