Patents by Inventor Raphael Robert

Raphael Robert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240224049
    Abstract: A computer-implemented method, in a communication framework in which each of a plurality of users has one or more devices associated therewith, and in which the users use at least some of their devices to communicate via a backend system. A first user has a first set of first one or more associated trusted devices, and a second user has a second set of second one or more trusted devices associated therewith. The first user forms a first cryptographic trust relationship between a first device in the first set and a second device in the second set. Based on (i) the first cryptographic trust relationship, and (ii) the second set associated with the second user, the first user forms corresponding second cryptographic trust relationships between each device in the first set and each device in the second set. A least one device in the first set communicates with one or more devices in the second set based on the second trust relationship.
    Type: Application
    Filed: November 3, 2023
    Publication date: July 4, 2024
    Applicant: Wire Swiss GmbH
    Inventor: Raphael Robert
  • Patent number: 11849328
    Abstract: A computer-implemented method, in a communication framework in which each of a plurality of users has one or more devices associated therewith, and in which the users use at least some of their devices to communicate via a backend system. A first user has a first set of first one or more associated trusted devices, and a second user has a second set of second one or more trusted devices associated therewith. The first user forms a first trust relationship between a first device in the first set and a second device in the second set. Based on (i) the first trust relationship, and (ii) the second set associated with the second user, the first user forms a second trust relationship between each device in the first set and each device in the second set. A least one device in the first set communicates with one or more devices in the second set based on the second trust relationship.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: December 19, 2023
    Assignee: Wire Swiss GmbH
    Inventor: Raphael Robert
  • Publication number: 20210044968
    Abstract: A computer-implemented method, in a communication framework in which each of a plurality of users has one or more devices associated therewith, and in which the users use at least some of their devices to communicate via a backend system. A first user has a first set of first one or more associated trusted devices, and a second user has a second set of second one or more trusted devices associated therewith. The first user forms a first trust relationship between a first device in the first set and a second device in the second set. Based on (i) the first trust relationship, and (ii) the second set associated with the second user, the first user forms a second trust relationship between each device in the first set and each device in the second set. A least one device in the first set communicates with one or more devices in the second set based on the second trust relationship.
    Type: Application
    Filed: March 14, 2019
    Publication date: February 11, 2021
    Applicant: Wire Swiss GmbH
    Inventor: Raphael Robert
  • Patent number: 8572298
    Abstract: An integrated circuit comprises a predefined logic area including a microprocessor coupled to a plurality of peripheral devices including an external bus interface over a system bus. A customizable logic area is accessible by the microprocessor over the system bus. A first I/O bus sends data to an external device. A second I/O bus receives data from an external device. A first set of multiplexers in the predefined logic area have first inputs coupled to an output of the external bus interface, second inputs coupled to the customizable logic area, and an output coupled to a first I/O bus. A second set of multiplexers in the predefined logic area have first inputs coupled to the customizable logic area, second inputs coupled to the second I/O bus, and an output coupled to an input of the external bus interface.
    Type: Grant
    Filed: January 29, 2007
    Date of Patent: October 29, 2013
    Assignee: Atmel Corporation
    Inventors: Alain Vergnes, Raphael Robert
  • Publication number: 20080244131
    Abstract: An integrated multibus system includes a first and second master devices coupled to first and second master busses. A slave device is coupled to the first and second master busses through a first multiplexer, a first address decoder coupled to the first master bus having an output associated with the slave device, a second address decoder coupled to the second master bus and having an output associated with the slave device. A first arbiter circuit multiplexer has an output coupled to a select input of the first multiplexer. A first arbiter circuit is coupled to the outputs of the first and second address decoders, the first arbiter circuit having an output that is a predetermined function of the address decoder outputs and is coupled to an input of the first arbiter circuit multiplexer. A configurable logic area has a first net coupled to an input of the arbiter circuit multiplexer.
    Type: Application
    Filed: March 26, 2007
    Publication date: October 2, 2008
    Applicant: ATMEL CORPORATION
    Inventors: Alain Vergnes, Raphael Robert
  • Publication number: 20080183938
    Abstract: An integrated circuit comprises a predefined logic area including a microprocessor coupled to a plurality of peripheral devices including an external bus interface over a system bus. A customizable logic area is accessible by the microprocessor over the system bus. A first I/O bus sends data to an external device. A second I/O bus receives data from an external device. A first set of multiplexers in the predefined logic area have first inputs coupled to an output of the external bus interface, second inputs coupled to the customizable logic area, and an output coupled to a first I/O bus. A second set of multiplexers in the predefined logic area have first inputs coupled to the customizable logic area, second inputs coupled to the second I/O bus, and an output coupled to an input of the external bus interface.
    Type: Application
    Filed: January 29, 2007
    Publication date: July 31, 2008
    Applicant: ATMEL CORPORATION
    Inventors: Alain Vergnes, Raphael Robert