Abstract: A semiconductor junction may include a first semiconductor material and a second material. The first and the second semiconductor materials are extrinsically undoped. At least a portion of a valence band of the second material has a higher energy level than at least a portion of the conduction band of the first semiconductor material (type-III band alignment). A flow of a majority of free carriers across the semiconductor junction is diffusive. A region of generation and/or recombination of a plurality of free carriers is confined to a two-dimensional surface of the second material, and at the interface of the first semiconductor material and the second material.

Abstract: A semiconductor junction may include a first layer and a second layer. The first layer may include a first semiconductor material and the second layer may be deposited on the first layer and may include a second material. The valence band maximum of the second material is higher than a conduction band minimum of the first semiconductor material, thereby allowing a flow of a majority of free carriers across the semiconductor junction between the first and second layers to be diffusive.

Abstract: Graphene is used as an interfacial layer to grow Si and other semiconductors or crystalline materials including two-dimensional Si and other structures on any foreign substrate that can withstand the growth temperature without the limitation matching condition typically required for epitaxial growth.

Abstract: Graphene is used as an interfacial layer to grow Si and other semiconductors or crystalline materials including two-dimensional Si and other structures on any foreign substrate that can withstand the growth temperature without the limitation matching condition typically required for epitaxial growth.

Abstract: Graphene is used as an interfacial layer to grow Si and other semiconductors or crystalline materials including two-dimensional Si and other structures on any foreign substrate that can withstand the growth temperature without the limitation matching condition typically required for epitaxial growth.

Abstract: A semiconductor junction may include a first layer and a second layer. The first layer may include a first semiconductor material and the second layer may be deposited on the first layer and may include a second material. The valence band maximum of the second material is higher than a conduction band minimum of the first semiconductor material, thereby allowing a flow of a majority of free carriers across the semiconductor junction between the first and second layers to be diffusive.

Abstract: Graphene is used as an interfacial layer to grow Si and other semiconductors or crystalline materials including two-dimensional Si and other structures on any foreign substrate that can withstand the growth temperature without the limitation matching condition typically required for epitaxial growth.

Abstract: A semiconductor junction may include a first semiconductor material and a second material. The first and the second semiconductor materials are extrinsically undoped. At least a portion of a valence band of the second material has a higher energy level than at least a portion of the conduction band of the first semiconductor material (type-III band alignment). A flow of a majority of free carriers across the semiconductor junction is diffusive. A region of generation and/or recombination of a plurality of free carriers is confined to a two-dimensional surface of the second material, and at the interface of the first semiconductor material and the second material.

Abstract: A multilayered structure is provided. The multilayered structure may include a silicon substrate and a film of gadolinium oxide disposed on the silicon substrate. The top surface of the silicon substrate may have silicon orientated in the 100 direction (Si(100)) and the gadolinium oxide disposed thereon may have an orientation in the 100 direction (Gd2O3(100)).

Abstract: A multilayered structure is provided. The multilayered structure may include a silicon substrate and a film of gadolinium oxide disposed on the silicon substrate. The top surface of the silicon substrate may have silicon orientated in the 100 direction (Si(100)) and the gadolinium oxide disposed thereon may have an orientation in the 100 direction (Gd2O3(100)).

Abstract: A multilayered structure is provided. The multilayered structure may include a silicon substrate and a film of gadolinium oxide disposed on the silicon substrate. The top surface of the silicon substrate may have silicon orientated in the 100 direction (Si(100)) and the gadolinium oxide disposed thereon may have an orientation in the 100 direction (Gd2O3(100)).

Abstract: A multilayered structure is provided. The multilayered structure may include a silicon substrate and a film of gadolinium oxide disposed on the silicon substrate. The top surface of the silicon substrate may have silicon orientated in the 100 direction (Si(100)) and the gadolinium oxide disposed thereon may have an orientation in the 100 direction (Gd2O3(100)).

Abstract: A method for producing an insulating or barrier layer (FIG. 1B), useful for semiconductor devices, comprises depositing a layer of silicon and at least one additional element on a silicon substrate whereby said deposited layer is substantially free of defects such that epitaxial silicon substantially free of defects can be deposited on said deposited layer. Alternatively, a monolayer of one or more elements, preferably comprising oxygen, is absorbed on a silicon substrate. A plurality of insulating layers sandwiched between epitaxial silicon forms a barrier composite. Semiconductor devices are disclosed which comprise said barrier composite.

Abstract: A Si/C superlattice useful for semiconductor devices comprises a plurality of epitaxially grown silicon layers alternating with carbon layers respectively adsorbed on surfaces of said silicon layers. Structures and devices comprising the superlattice and methods are described.

Abstract: A method for producing an insulating or barrier layer (FIG. 1B), useful for semiconductor devices, comprises depositing a layer of silicon and at least one additional element on a silicon substrate whereby said deposited layer is substantially free of defects such that epitaxial silicon substantially free of defects can be deposited on said deposited layer. Alternatively, a monolayer of one or more elements, preferably comprising oxygen, is absorbed on a silicon substrate. A plurality of insulating layers sandwiched between epitaxial silicon forms a barrier composite. Semiconductor devices are disclosed which comprise said barrier composite.

Abstract: A Si/C superlattice useful for semiconductor devices comprises a plurality of epitaxially grown silicon layers alternating with carbon layers respectively adsorbed on surfaces of said silicon layers. Structures and devices comprising the superlattice and methods are described.

Abstract: A method for producing an insulating or barrier layer, useful for semiconductor devices, comprises depositing a layer of silicon and at least one additional element on said silicon substrate whereby said deposited layer is substantially free of defects such that epitaxial silicon substantially free of defects can be deposited on said deposited layer. Alternatively, a monolayer of one or more elements, preferably comprising oxygen, is absorbed on a silicon substrate. A plurality of insulating layers sandwiched between epitaxial silicon forms a barrier composite. Semiconductor devices are disclosed which comprise said barrier composite.

Abstract: A solid state electronic device exhibiting negative differential resistance is fabricated by depositing a thin layer of amorphous silicon on a single crystal substrate, doped N+. The amorphous silicon is simultaneously crystallized and oxidized in a dry N2 and O2 mixture. The result is a layer of amorphous SiO2 surrounding microclusters of crystalline silicon. A layer of polycrystalline silicon is deposited to a thickness of approximately 0.5 micron. Ohmic metal contacts are made to the top and bottom. These active layers are isolated by insulating SiO2. A bias voltage applied between the metal contacts results in negative differential resistance due to tunneling through resonant energy levels in microclusters.

Abstract: A solid state electronic device exhibiting negative differential resistance s fabricated by depositing a thin layer of amorphous silicon on a single crystal substrate, doped N.sup.+. The amorphous silicon is simultaneously crystallized and oxidized in a dry N.sub.2 and O.sub.2 mixture. The result is a layer of amorphous Sio.sub.2 surrounding microclusters of crystalline silicon. A layer of polycrystalline silicon is deposited to a thickness of approximately 0.5 micron. Ohmic metal contacts are made to the top and bottom. These active layers are isolated by insulating SiO.sub.2. A bias voltage applied between the metal contacts results in negative differential resistance due to tunneling through resonant energy levels in microclusters.

Abstract: The invention provides light sources which are easily compatible with standard silicon VLSI processing and can be located directly in the material of the silicon VLSI chip. P-type silicon substrate is processed to produce proturbances, the proturbances preferably having tip dimensions on the order of 5-10 mm. A native oxide film (SiO.sub.2) is caused to develop on the surface of the silicon substrate. A thin, transparent, conductive film is then deposited on top of the SiO.sub.2. Electrical contacts are made to the top of the conductive film and to the bottom of the silicon substrate. The carriers for electroluminescence are supplied by the P-doped silicon substrate (holes) and the conductive film (electrons). When a voltage is applied across the layers via the electrical contacts, the holes are concentrated in the region of the tip of the proturbances because the electric field lines concentrate near a pointed object, and electron current across the SiO.sub.