Patents by Inventor Raqiang Bao

Raqiang Bao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Replacement metal gate scheme with self-alignment gate for vertical field effect transistors
    Patent number: 10355106
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming a fin structure over a substrate, forming a dummy gate over the fin structure, and etching the dummy gate by a first amount to expose a top portion of the fin structure. The method further includes forming a first dielectric layer adjacent the exposed top portion of the fin structure, forming a spacer adjacent the first dielectric layer contacting the fin structure, and etching the dummy gate by a second amount. The method further includes depositing a second dielectric layer to encapsulate the remaining dummy gate, depositing an inter-level dielectric (ILD) over the second dielectric layer, depositing at least one hard mask to access the dummy gate, stripping the dummy gate to form at least one recess, and filling the at least one recess with a high-k metal gate (HKMG).
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Raqiang Bao, Dechao Guo
  • REPLACEMENT METAL GATE SCHEME WITH SELF-ALIGNMENT GATE FOR VERTICAL FIELD EFFECT TRANSISTORS
    Publication number: 20180254330
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming a fin structure over a substrate, forming a dummy gate over the fin structure, and etching the dummy gate by a first amount to expose a top portion of the fin structure. The method further includes forming a first dielectric layer adjacent the exposed top portion of the fin structure, forming a spacer adjacent the first dielectric layer contacting the fin structure, and etching the dummy gate by a second amount. The method further includes depositing a second dielectric layer to encapsulate the remaining dummy gate, depositing an inter-level dielectric (ILD) over the second dielectric layer, depositing at least one hard mask to access the dummy gate, stripping the dummy gate to form at least one recess, and filling the at least one recess with a high-k metal gate (HKMG).
    Type: Application
    Filed: May 4, 2018
    Publication date: September 6, 2018
    Inventors: Raqiang Bao, Dechao Guo
  • REPLACEMENT METAL GATE SCHEME WITH SELF-ALIGNMENT GATE FOR VERTICAL FIELD EFFECT TRANSISTORS
    Publication number: 20180226493
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming a fin structure over a substrate, forming a dummy gate over the fin structure, and etching the dummy gate by a first amount to expose a top portion of the fin structure. The method further includes forming a first dielectric layer adjacent the exposed top portion of the fin structure, forming a spacer adjacent the first dielectric layer contacting the fin structure, and etching the dummy gate by a second amount.
    Type: Application
    Filed: November 6, 2017
    Publication date: August 9, 2018
    Inventors: Raqiang Bao, Dechao Guo
  • Replacement metal gate scheme with self-alignment gate for vertical field effect transistors
    Patent number: 10043891
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming a fin structure over a substrate, forming a dummy gate over the fin structure, and etching the dummy gate by a first amount to expose a top portion of the fin structure. The method further includes forming a first dielectric layer adjacent the exposed top portion of the fin structure, forming a spacer adjacent the first dielectric layer contacting the fin structure, and etching the dummy gate by a second amount. The method further includes depositing a second dielectric layer to encapsulate the remaining dummy gate, depositing an inter-level dielectric (ILD) over the second dielectric layer, depositing at least one hard mask to access the dummy gate, stripping the dummy gate to form at least one recess, and filling the at least one recess with a high-k metal gate (HKMG).
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Raqiang Bao, Dechao Guo
  • Replacement metal gate scheme with self-alignment gate for vertical field effect transistors
    Patent number: 9960254
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming a fin structure over a substrate, forming a dummy gate over the fin structure, and etching the dummy gate by a first amount to expose a top portion of the fin structure. The method further includes forming a first dielectric layer adjacent the exposed top portion of the fin structure, forming a spacer adjacent the first dielectric layer contacting the fin structure, and etching the dummy gate by a second amount. The method further includes depositing a second dielectric layer to encapsulate the remaining dummy gate, depositing an inter-level dielectric (ILD) over the second dielectric layer, depositing at least one hard mask to access the dummy gate, stripping the dummy gate to form at least one recess, and filling the at least one recess with a high-k metal gate (HKMG).
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: May 1, 2018
    Assignee: International Business Machines Corporation
    Inventors: Raqiang Bao, Dechao Guo