Patents by Inventor Raquel Lara dos Santos Pereira

Raquel Lara dos Santos Pereira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10796051
    Abstract: In the described examples, a model impact monitor can include an electronic design automation (EDA) manager that communicates with a plurality of EDA programs, wherein each EDA program generates a model set for a register-transfer level (RTL) design comprising a list of RTL operations. The model impact monitor can also include an adaptive model interface that records changes to the RTL operations of the RTL design and measures a change in performance characteristics of each of the plurality of EDA programs based on a respective one of the changes in the RTL operations of the RTL design.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: October 6, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Abner Luis Panho Marciano, Matheus Fonseca, Thamara Karen Cunha Andrade, Raquel Lara dos Santos Pereira, Fabiano Cruz Peixoto, Rodolfo Santos Teixeira, Rafael Gontijo Hamdan, Bruno Andrade Pereira
  • Patent number: 10706195
    Abstract: The present disclosure relates to a method for use in the formal verification of an electronic circuit. Embodiments may include receiving, using a processor, a portion of an electronic circuit design and analyzing a syntactic structure of a string associated with the electronic circuit design. Embodiments may also include generating a parse tree, based upon, at least in part, the analysis and traversing the parse tree to identify one or more conditional nodes. Embodiments may further include generating a new node for each of the one or more conditional nodes and displaying, at a graphical user interface, a check, at least one of the one or more conditional nodes or the new node prior to performing either register-transfer-level RTL synthesis or final synthesis.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: July 7, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Luis Humberto Rezende Barbosa, Raquel Lara dos Santos Pereira, Caio Alves Furtado, Breno Augusto Dias Vitorino, Mirlaine Aparecida Crepalde, Rodrigo da Silva Mantini Viana, Lucas Duarte Prates
  • Patent number: 9858372
    Abstract: Disclosed are techniques for implementing formal verification of an electronic design. These techniques identify a target property for verification in a hierarchical electronic design that has a plurality of hierarchies and perform hierarchical synthesis on a hierarchy or a portion thereof in the plurality of hierarchies while black-boxing a remaining portion of the hierarchical electronic design. Cone of influence (COI) data that is relevant to the target property may be determined at least by extracting the cone of influence data from a hierarchically synthesized hierarchy or portion of the hierarchy or the portion thereof. At least the cone of influence data may be forwarded to a formal engine that uses the cone of influence data to verify the target property.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: January 2, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hudson Dyele Oliveira, Abner Luis Panho Marciano, Guilherme Seminotti Braga, Caio Texeira Campos, Breno Rodrigues Guimares, Rodrigo Fonseca Rocha Soares, Laiz Lipiainen Santos, Raquel Lara dos Santos Pereira, Adriana Cassia Rossi de Almeida Braz