Abstract: An apparatus to facilitate tessellation redistribution for reducing latencies in processors is disclosed. The apparatus includes a processor to provide parallel interconnected geometry fixed-function units with separate front end and back ends, the front ends to perform patch culling and transmission and the back ends to perform patch reception from the front end and patch tessellation; provide a tessellation redistribution central engine to redistribute patches among the back ends using a redistribution bus; receive, by the tessellation redistribution central engine from the front ends in parallel, patch transmissions marked for distribution, the tessellation redistribution engine to process the patch transmissions in order; and in response to receiving a synchronization barrier packet from one of the front ends, broadcast, by the tessellation redistribution central engine, the synchronization barrier packet to the back ends to cause one of the back ends to process tessellation work locally.

Abstract: An apparatus to facilitate tessellation redistribution for reducing latencies in processors is disclosed. The apparatus includes a processor to provide parallel interconnected geometry fixed-function units with separate front end and back ends, the front ends to perform patch culling and transmission and the back ends to perform patch reception from the front end and patch tessellation; provide a tessellation redistribution central engine to redistribute patches among the back ends using a redistribution bus; receive, by the tessellation redistribution central engine from the front ends in parallel, patch transmissions marked for distribution, the tessellation redistribution engine to process the patch transmissions in order; and in response to receiving a synchronization barrier packet from one of the front ends, broadcast, by the tessellation redistribution central engine, the synchronization barrier packet to the back ends to cause one of the back ends to process tessellation work locally.

Abstract: An apparatus to facilitate tessellation redistribution for reducing latencies in processors is disclosed. The apparatus includes a processor to provide parallel interconnected geometry fixed-function units with separate front end and back ends, the front ends to perform patch culling and transmission and the back ends to perform patch reception from the front end and patch tessellation; provide a tessellation redistribution central engine to redistribute patches among the back ends using a redistribution bus; receive, by the tessellation redistribution central engine from the front ends in parallel, patch transmissions marked for distribution, the tessellation redistribution engine to process the patch transmissions in order; and in response to receiving a synchronization barrier packet from one of the front ends, broadcast, by the tessellation redistribution central engine, the synchronization barrier packet to the back ends to cause one of the back ends to process tessellation work locally.