Patents by Inventor Rashmi D. Chatty
Rashmi D. Chatty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10169500Abstract: Embodiments of the invention provide a method, system, and program product for predicting a delay of a critical path. In one embodiment, the invention provides a method of predicting a delay of at least one critical path of an integrated circuit, the method comprising: determining a delay of at least one ring oscillator on the integrated circuit; and calculating a predicted delay for the at least one critical path delay based on a delay of components of the critical path at a corner condition, a wire delay of the at least one critical path, a delay of the at least one ring oscillator at a corner condition, and the determined delay of the at least one ring oscillator.Type: GrantFiled: August 8, 2011Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Margaret R. Charlebois, Rashmi D. Chatty, Christopher D. Hanudel, Robert D. Herzl, David W. Milton, Clarence R. Ogilvie, Matthew P. Szafir, Tad J. Wilder
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Patent number: 8754696Abstract: Aspects of the invention provide a circuit structure that automatically monitors a plurality of ring oscillators and dynamically selects the fastest or the slowest ring oscillator for feedback into the plurality of ring oscillators. In one embodiment, a circuit includes: a plurality of delay elements, each delay element associated with a ring oscillator; a first logic gate for receiving outputs of each of the delay elements; a second logic gate for receiving outputs of each of the delay elements; and a multiplexer for receiving an output of the first logic gate and an output of the second logic gate and choosing one of the outputs, wherein a selection for the multiplexer is based on an output of the multiplexer. To select the fastest ring oscillator, a second multiplexer is provided.Type: GrantFiled: July 26, 2012Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Margaret R. Charlebois, Rashmi D. Chatty, Christopher D. Hanudel, Robert D. Herzl, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely, Matthew P. Szafir, Tad J. Wilder
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Publication number: 20140028365Abstract: Aspects of the invention provide a circuit structure that automatically monitors a plurality of ring oscillators and dynamically selects the fastest or the slowest ring oscillator for feedback into the plurality of ring oscillators. In one embodiment, a circuit includes: a plurality of delay elements, each delay element associated with a ring oscillator; a first logic gate for receiving outputs of each of the delay elements; a second logic gate for receiving outputs of each of the delay elements; and a multiplexer for receiving an output of the first logic gate and an output of the second logic gate and choosing one of the outputs, wherein a selection for the multiplexer is based on an output of the multiplexer. To select the fastest ring oscillator, a second multiplexer is provided.Type: ApplicationFiled: July 26, 2012Publication date: January 30, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Margaret R. Charlebois, Rashmi D. Chatty, Christopher D. Hanudel, Robert D. Herzl, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely, Matthew P. Szafir, Tad J. Wilder
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Publication number: 20130041608Abstract: Embodiments of the invention provide a method, system, and program product for predicting a delay of a critical path. In one embodiment, the invention provides a method of predicting a delay of at least one critical path of an integrated circuit, the method comprising: determining a delay of at least one ring oscillator on the integrated circuit; and calculating a predicted delay for the at least one critical path delay based on a delay of components of the critical path at a corner condition, a wire delay of the at least one critical path, a delay of the at least one ring oscillator at a corner condition, and the determined delay of the at least one ring oscillator.Type: ApplicationFiled: August 8, 2011Publication date: February 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Margaret R. Charlebois, Rashmi D. Chatty, Christopher D. Hanudel, Robert D. Herzl, David W. Milton, Clarence R. Ogilvie, Matthew P. Szafir, Tad J. Wilder
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Publication number: 20090112352Abstract: A storage medium including a method of modeling yield for semiconductor products includes determining expected faults for each of a plurality of library elements by running a critical area analysis on each of the library elements, and assessing, from the critical area analysis, an expected number of faults per unit area, and comparing the same to actual observed faults on previously manufactured semiconductor products. Thereafter, the expected number of faults for each library element is updated in response to observed yield. A database is established, which includes the die size and expected faults for each of the library elements. Integrated circuit product die size is estimated, and library elements to be used to create the integrated circuit die are selected. Fault and size data for each of the selected library elements are obtained, the adjusted estimated faults for each of the library elements are summed, and estimated yield is calculated.Type: ApplicationFiled: January 5, 2009Publication date: April 30, 2009Applicant: International Business Machines CorporationInventors: Thomas S. Barnett, Jeanne P. Bickford, William Y. Chang, Rashmi D. Chatty, Sebnem Jaji, Kerry A. Kravec, Wing L. Lai, Gie Lee, Brian M. Trapp, Alan J. Weger
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Patent number: 7477961Abstract: A method of modeling yield for semiconductor products includes determining expected faults for each of a plurality of library elements by running a critical area analysis on each of the library elements, and assessing, from the critical area analysis, an expected number of faults per unit area, and comparing the same to actual observed faults on previously manufactured semiconductor products. Thereafter, the expected number of faults for each library element is updated in response to observed yield. A database is established, which includes the die size and expected faults for each of the library elements. Integrated circuit product die size is estimated, and library elements to be used to create the integrated circuit die are selected. Fault and size data for each of the selected library elements are obtained, the adjusted estimated faults for each of the library elements are summed, and estimated yield is calculated.Type: GrantFiled: May 12, 2006Date of Patent: January 13, 2009Assignee: International Business Machines CorporationInventors: Thomas S. Barnett, Jeanne P. Bickford, William Y. Chang, Rashmi D. Chatty, Sebnem Jaji, Kerry A. Kravec, Wing L. Lai, Gie Lee, Brian M. Trapp, Alan J. Weger